Media Alert: Open-Silicon to Present at TSMC OIP Theater at DAC 2018

MILPITAS, Calif., June 21, 2018 (GLOBE NEWSWIRE) -- Open-Silicon, a system-optimized ASIC solution provider and long-standing member of TSMC’s Value Chain Aggregator (VCA) and Design Center Alliance (DCA) programs, will present on three topics at the TSMC Open Innovation Platform® (OIP) Theater at DAC 2018 in San Francisco. The presentations will address how increases in cores, bandwidth and data in deep learning and networking applications are driving the need for custom processors and ASIC SiPs with High Bandwidth Memory (HBM2). They will also provide an overview of the critical IP building blocks required for 2.5D HBM2 ASIC SiP design and manufacturing solutions. All presentations will take place at the TSMC OIP Theater in Booth 1629.  

  1. Who: Asim Salim, VP of Manufacturing Operations, Open-Silicon

    What: Turnkey 2.5D HBM2 ASIC SiP Solution for Deep Learning and Networking Applications

    This presentation will address the growing memory requirements for deep learning and networking applications, and how a silicon-proven HBM2 IP subsystem in TSMC’s FinFET and CoWoS® technologies is enabling these applications and successful ramping of 2.5D HBM2 ASIC SiP designs into volume production. 

    When: Monday, June 25, 2:15 – 2:30 p.m.

  1. Who: Kalpesh Sanghvi, Technical Manager for IP and Platforms, Open-Silicon

    What: IP Subsystem Solutions for Deep Learning and Networking Applications

    This presentation will address the key building blocks of deep learning and networking applications, including an HBM2 IP subsystem, a networking IP subsystem and a multi core processor IP subsystem including RISC-V targeted for TSMC’s advanced process technologies.

    When: Tuesday, June 26, 11:30 – 11:45 a.m.

  1. Who: Abu Eghan, Sr. Manager of Packaging & Assembly Operations, Open-Silicon

    What: Package Design, Assembly and Test Strategies for robust 2.5D HBM2 ASIC SiP Manufacturing

    This presentation will address solutions and strategies for mitigating the interposer design, package design, assembly and test challenges associated with 2.5D HBM2 ASIC SiP manufacturing in TSMC’s FinFET and CoWoS® technologies.

    When: Wednesday, June 27, 3:30 – 3:45 p.m.

About Open-Silicon

Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, visit www.open-silicon.com

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.

Contact Information:
Purvi Shenoy
Open-Silicon
408-240-5772
Email Contact

Media Contact:
Jennifer DeAnda
208-794-7113
Email Contact

 

Primary Logo

Featured Video
Jobs
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
CAD Engineer for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise