SAN JOSE, CA--(Marketwired - May 09, 2017) - Andes Technology Corporation, the leading Asia-based supplier of high performance, low-power, small embedded CPU cores serving 2-billion SoCs, today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley. Andes ISA, called AndeStar™ V5, supports 64-bits and the widely known RISC-V ISA as its subset and will bring the open, compact, and modular RISC-V into mainstream SoC applications. The AndeStar infrastructure, evolved over the past 12 years includes advanced features such as CoDense™, PowerBrake, and StackSafe™, and application-specific architecture extensions such as Custom Extensions, DSP Extensions and Security Extensions, in addition to strong compiler optimizations for the optimal performance and code size. Adding 64-bit capabilities to Andes existing families of IP cores will satisfy new SoC's requirement for addressing memory over 4GB in applications such as high capacity storages, large-scale networks, deep learning and AI systems. Leveraging Andes' history of industry leading performance-to-power ratio, SoCs with AndeStar™ V5 based cores will be able to run efficiently at high frequency. For example, the new V5 AndesCore™ NX25 in a typical configuration will deliver over 1GHz (in "worst case" conditions) with area of only 67K gates and with power consumption as little as 17 µW/MHz in a TSMC 28nm process.

"Time-to-market is a major concern in every SoC design and one task that slows design progress is writing RTL code simply to integrate a collection of standard IP blocks and then spending an equal or greater amount of time verifying the new code," said Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior Vice President of R&D. "With the new AndeStar™ V5 architecture, we provide a complete solution for 64-bit embedded SoC designs by bringing RISC-V compliance together with Andes' successful line of AndeStar™ V3 IP cores, convenient features (such as CoDense, PowerBrake and StackSafe) and architecture extensions (such as Custom Extensions, DSP Extensions and Security Extensions), standard Andes IDE software toolchain with comprehensive extended features, SoC peripherals, hardware developing platforms, service and support. Collectively, this helps to satisfy needs of design teams by significantly improving the product quality and reducing time-to-market and risk for production-ready 64-bit SoC designs. When Andes started to plan AndeStar™ V5, we considered the full scope of supporting an extended ISA, enabling customers to leverage fertile RISC-V ecosystem while maintaining the strengths we accumulated over time."

Differentiation of AndeStar™ V5 Solution

Andes is the first mainstream CPU IP provider to adopt RISC-V. The AndeStar™ V5 architecture is fully compliant with RISC-V while bringing extended (superset) features unique to Andes and providing full support of the AndeSight IDE development tools. This approach offers customers a way to develop 64-bit software in the same convenient environment as in V3. In addition, the powerful Andes Custom Extension™ (ACE) environment greatly simplifies the task of extending application-accelerating instructions for V5 by automatically generating all necessary development tools and housekeeping RTL code, and automatically verifying custom logic against its defined behavior. Furthermore, products based on AndeStar™ V5 will support the extensive line of silicon-proven Andes SoC peripherals including the Andes System Control Platform and have the benefit of Andes extensive validation for use with industry-standard EDA tool and libraries. Furthermore, AndeStar™ V5 provides support for addressability of greater than 4GB, AXI 64-bit interface, GCC compiler and GDB debugger which had being validated by strict industrial and Open Source test suites. Therefore AndeStar™ V5 is the comprehensive solution for customers to achieve optimum performance for their products and to shorten their development cycle.

Availability