R-STRATUS-LP SILICON IP REDUCES SIGNIFICANTLY POWER CONSUMPTION OF FLASH MEMORIES

Grenoble, France - February 06, 2017 - Connected battery-based devices require always more computing power to run feature rich application programs while using the minimal energy to ensure the longest usage without recharge. As a result, fabless companies need to hunt down every "mA" to satisfy the low-power expectations of their SoC users.

Numerous System-on-Chips rely on a Non-Volatile flash Memory - either embedded or external - to store the application program as it provides an easy firmware update whenever needed. A quick analysis shows that each access to the flash memory requires a significant amount of energy, thus providing room for appealing savings. At the same time, the main challenge for SoC designers is that application program characteristics are unknown in most cases at the date of SoC design-in, making any performance optimization challenging.

R-Stratus-LP is the first cache controller silicon IP optimized to address these low-power challenges. It indeed relies on an innovative architecture which reduces drastically the number of flash accesses, by up to 1,000 times, whatever the targeted CPU frequency, while enabling on-the-fly reconfiguration of relevant cache parameters for specific application program characteristics so as to achieve ultimate power savings.

Benchmarking shows that an embedded flash memory subsystem relying on R-Stratus-LP consumes up to 3x less power than a flash memory connected to an MCU with a prefetch system. Such power savings are even more impressive with external flash memories as R-Stratus-LP allows running code directly from a flash memory (Execute-In-Place, XIP). Comparisons with other cache controllers also demonstrate that power consumption may be minimized thanks to R-Stratus-LP while using a cache memory of much lower capacity, thus enabling both area and power consumption savings for the same data throughput.

As selection of the appropriate values for cache parameters may be a burden for SoC designers, this innovative cache controller IP is provided with an EDA solution which allows easily identifying the best cache controller settings.

Featured Video
Jobs
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise