MILPITAS, CA--(Marketwired - September 28, 2016) - Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully taped out the industry's first High Bandwidth Memory (HBM2) IP subsystem in TSMC's 16nm FF+ process in combination with TSMC's CoWoS® 2.5D silicon interposer technology. This full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, all developed in-house, and completes the critical components needed for the successful integration of HBM2 memory into ASIC system-in-package (SiP) designs. The HBM2 IP subsystem solution is available for 2.5D ASIC design starts and also as a licensable Intellectual Property (IP) subsystem.

Open-Silicon's IP fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The high performance, low latency controller leverages the HBM parallel architecture and protocol efficiency to achieve maximum bandwidth. The IP includes a scalable and optimized PHY and die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer.

Open-Silicon's HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue-isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement while ramping HBM2 ASIC designs into volume production.

Open-Silicon's HBM2 solution in 16nm FF+ features 2Gbps per pin data rate at up to 5mm trace length. This enables a full 8-channel connection from a 16nm SoC to a single HBM2 memory stack at 2Gbps, achieving bandwidths up to 256GB/s. Open-Silicon will continue its work in this area to achieve even higher HBM2 data rates (2.4Gbps per pin data rate), as well as HBM3.

"Open-Silicon has extensive experience in 2.5D ASIC design as well as other high-bandwidth chip-to-chip and chip-to-memory interface IP and ASIC solutions. This tapeout is a significant step in enabling the next generation of high bandwidth applications in networking, deep learning, virtual reality, gaming, cloud computing and data centers. This achievement, along with HBM2 ASIC customer design wins, testifies to the commitment and capability of our IP and ASIC design teams," said Taher Madraswala, President and CEO at Open-Silicon.

"Open-Silicon's tapeout of an HBM2 IP subsystem in 16nm is a significant milestone in demonstrating that the HBM ecosystem is ready to supply HBM2 ASIC SiPs," said Herb Reiter, President, eda2asic Consulting, Inc. and author of the most recent Multi-Die IC User Guide, co-sponsored by the Electronic System Design Alliance (ESD Alliance). "Turnkey ASIC vendors, like Open-Silicon, with experience in interposer-based IC and system design with HBM, are key elements of enabling the supply of fully tested HBM ASIC SiPs."

For more information, visit www.open-silicon.com/high-bandwidth-memory-ip

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