MILPITAS, CA--(Marketwired - September 14, 2016) - Open-Silicon invites you to join others in the semiconductor design community to learn more about the company's broad portfolio of ASIC solutions at the TSMC Open Innovation Platform (OIP) Ecosystem Forum, September 22, 2016, San Jose McEnery Convention Center, San Jose, CA. Open-Silicon will demonstrate its latest ASIC solutions and present a technical paper on HBM IP subsystem implementation for 2.5D ASIC design. Additionally, as an ARM DesignStart Approved Design Partner, Open-Silicon will be exhibiting its Spec2Chip IoT ASIC platform at the ARM 'Connected World of Opportunity' booth, located in the Ecosystem Pavilion, from 1:00 p.m. to 6:30 p.m.

Paper Presentation:

• HBM IP Subsystem Implementation: 2.5D ASIC
  11:30 - 12:00 - IP/EDA/Services Track
  During this presentation, Open-Silicon will present its HBM-Gen2 IP subsystem in TSMC's 16nm FF+ process in combination with TSMC's CoWoS® 2.5D silicon-interposer technology. Aspects to be discussed include HBM applications, HBM IP subsystem solution (controller PHY and die-to-die interposer-IO) implementation, as well as the integration challenges of IP for 2.5D ASIC implementation.

Demonstrations/Solutions:
Exhibit Booth #604
08:00 - 18:30 - Ecosystem Pavilion

• HBM Gen2 IP Subsystem Solution - This solution is now available for 2.5D ASIC design starts and also as licensable Intellectual Property (IP). Open-Silicon's IP fully complies with the HBM-Gen2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The IP includes the PHY and custom die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer.
• IoT ASIC Platform - Demonstrates end-to-end communication between sensor hubs and a cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. This Industrial IoT system setup is part of Open-Silicon's Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at the system level.
• 28G SerDes Evaluation Platform - Enables the rapid deployment of chips and systems for high-bandwidth networks. The platform includes a full board with a packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
• HMC 2.0 Memory Controller ASIC IP Platform - Allows quick evaluation of the HMC technology and performance testing of the HMC links. Based on the Xilinx Virtex-7 FPGA, this platform includes a fully validated design that integrates HMC controller exerciser functions.