Cadence Announces Availability of Complete IC Packaging Design and Analysis Solutions for Advanced Fan-Out Wafer-Level Chip Scale Packaging

Cross-fabric optimization accelerates multi-chip integration for smaller, lighter, power-optimized wireless mobile devices

SAN JOSE, Calif., March 14, 2016 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry's only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.

Cadence Logo.

This complete IC packaging design and analysis solution includes the Cadence® OrbitIOTM  Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS). This set of offerings enables multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.

The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance. For more information on the Cadence IC packaging design and analysis solution, visit http://www.cadence.com/news/ICpackaging172.

"Wireless mobility and wireless-enabled is the trend at all levels of electronic-centric products, from smartphones to cars to home appliances and beyond. They all need thin, lightweight, low-power yet high-performance devices at their core. This is the sweet spot for WLCSP, fueling its predicted explosion in adoption," said Steve Durrill, senior product engineering group director for the PCB Group at Cadence. "Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and OrbitIO is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/cadence-announces-availability-of-complete-ic-packaging-design-and-analysis-solutions-for-advanced-fan-out-wafer-level-chip-scale-packaging-300234978.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com

Featured Video
Jobs
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise