RFEL adds new features to latest version of its award-winning ChannelCore Flex advanced Channeliser IP core

Newport, Isle of Wight, UK, February 22, 2016 - RFEL continues to enhance its multi-award winning, advanced channeliser IP core, ChannelCore Flex™. The latest version has many new features that ensure it continues to provide highly versatile, state-of-the-art solutions for a wide range of demanding channelisation applications such as communications, intercept, electronic warfare, security, industrial applications, COMINT, SIGINT, sonar, radio astronomy, research and software-defined radio.

One of the important new features is the option of VITA 49 compatible precision time-stamping of the output channelised data. This time-stamping is provided to 5ns accuracy or better on request.  The core receives time-stamped ADC data and provides a dynamic, compensated time-stamp with the output data for each channel. 

The input stage has been enhanced, now with support for up to four inputs giving improved application flexibility. An input buffer provides flow control for supporting network sourced baseband data.  The input sample rate and FPGA clock rate are decoupled with the maximum aggregate output channel sample rate now limited to the FPGA clock rate.  A front-end frequency mixer stage allows for global frequency correction on each input channel, to counter effects like Doppler, for example, to accuracies much lower than 1 Hz. 

ChannelCore Flex™ uses a novel architecture to implement a large number of Digital Down Converter (DDC) channels very efficiently.  FPGA resources are used in proportion to the log of the number of channels enabling thousands of channels to be implemented in a moderately sized FPGA. 

Real-time, on-the-fly control is available for each channel to change the input source selection, centre frequency, sample rate, gain and filter response including bandwidth.  New in this latest release is the user programmable option to maintain phase coherency when reprogramming channels and the core is still capable of being phase coherent across multiple cores. 

Each channel path is normalised to map a full-scale input signal to half the dynamic range on the output giving output headroom and an internal gain stage provides up to 102 dB of gain per channel, which is adjustable at run-time. Each channel has excellent RF performance with SFDR of greater than 80 dBc, 80% Nyquist pass-band and a passband ripple of less than 0.1 dB.  The user can select either an Infinite Impulse Response (IIR) or the Finite Impulse Response (FIR) output filter stage to provide more effective filter response with reduced resource utilisation.

A powerful fractional rate resampler is provided on each channel, allowing resampling to sub-Hz accuracy, making ChannelCore Flex™ a unique solution that delivers unrivalled performance using a low power budget and highly effective use of FPGA resources.

RFEL can provide free, fully operational, fully featured cores to support system design and evaluation in either MATLAB® or ModelSim®.  These evaluation models operate for 60 minutes before reboot allowing time for extensive evaluation of the effectiveness of the design.  The time limitation is removed when the core is programmed with a key code that is provided when a full core license is purchased.

Available for Xilinx FPGAs with other devices on request, further data and pricing is available from RFEL now.

 



Read the complete story ...
Featured Video
Jobs
CAD Engineer for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise