Socionext to Highlight Leading Edge Technologies in Presentations at Design Automation Conference in San Francisco June 7-11

-- Emerging SoC Leader to Review its Latest Innovations in Conjunction with Cadence, Synopsys --

SUNNYVALE, Calif., June 3, 2015 — (PRNewswire) —  Socionext Inc., a new leader in advanced custom SoC design technology, will provide a series of presentations about its technology and innovations at the upcoming Design Automation Conference in San Francisco June 7-11. 

Socionext Inc. logo

As part of the DAC session schedule, Masato Tatsuoka of Socionext's Frontend Design Dept. will present "Physically-Aware High Level Synthesis Design Flow." He will propose a new approach on the routing congestion-aware high level synthesis design flow by integrating a HLS tool with physically-aware logic synthesis technology. This approach allows designers to resolve the congestion problems before proceeding to the layout design phase. He has applied this design flow to a large-scale production image processing design. The session is set for June 11 in room 307 at 1:30 pm.

Presentation at Cadence Theater

On June 9 in the Cadence Theater at booth 3515, Mr. Tatsuoka will present "Socionext Inc. High Level Synthesis: A Winning Technology." It will focus on how HLS can be applied to data path IP designs, and also control IP designs, such as DMAC, memory controllers and HEVC Encoder design. The presentation details the benefits of using HLS solutions to achieve first pass silicon in half the time required by traditional RTL design flow methodologies.

To achieve the goal, Socionext has worked with Cadence and introduced three key technologies in the design flow including interface-based design. The Socionext design flow also incorporates Micro-Architecture exploration and physically Aware HLS design flow to reduce risk in the backend. The session is scheduled for 5 pm.

Series of Presentations at Synopsys' Booth and Events

Several other presentations are also set. On June 8, Takuya Yasui, Manager, SoC Design Dept., will present "Transforming Product Deployment with 10X Faster Throughput in ICC Compiler II," at Synopsys' Compiler II Luncheon panel session in the Park Central Hotel starting at 11:30 am. On June 9 at Synopsys' Custom Design Luncheon panel event, Tadafumi Kadota, Senior Engineer of Socionext SoC Design Dept., will present "Adopting Synopsys Custom Designer for 3X TAT Improvement at Advanced Nodes." Both events are in Metropolitan Ballroom I of the hotel at 50 Third St. near Moscone Center.

Socionext will also deliver two presentations at the Synopsys Silicon-to-Software Theater in DAC booth 2133. On June 8 at 10:30 am Paul Little, Director of Technical Marketing, will present "Ever-increasing Bandwidth: High-performance SoC Solutions for Next-Generation Networks." On June 9 at 11 am Rajinder Cheema, Director of Marketing and Applications, High-Performance Business Division, will speak on the same topic.

For official DAC 2015 website and programs, visit www.dac.com.  

About Socionext Inc.

Socionext is a new, innovative enterprise that designs, develops and delivers System-on-Chip products to customers worldwide. The company is focused on imaging, networking and other dynamic technologies that drive today's leading-edge applications. Founded in 2015, Socionext Inc. is headquartered in Yokohama, and has offices in Japan, Asia, United States and Europe to lead its product development and sales activities. For more information, visit socionext.com.

For product information, visit the company's website at http://www.socionext.com, e-mail Email Contact or call 1-844-680-3453. For company news and updates, connect with us on Twitter ( https://www.twitter.com/socionextus) and Facebook ( https://www.facebook.com/socionextus)

Company and product names mentioned herein are trademarks or registered trademarks of their respective companies. Information provided in this press release is accurate at time of publication and subject to change without advance notice.

Logo - http://photos.prnewswire.com/prnh/20150402/196435LOGO

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/socionext-to-highlight-leading-edge-technologies-in-presentations-at-design-automation-conference-in-san-francisco-june-7-11-300093226.html

SOURCE Socionext Inc.

Contact:
Socionext Inc.
Sherry Chen, Socionext America Inc., 1-408-737-5654
Email Contact Dick Davies, IPRA, 1-415-652-7515
Email Contact
Web: http://www.socionext.com

Featured Video
Jobs
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise