Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite and backhaul markets. The IP core complements the company's broadest product portfolio of LDPC IP cores in the world.

ccsds ldpc decoderThe CCSDS LDPC codec supports code rate 223/255 with coded block size of 8160 bits, which allows for a simple replacement of legacy Reed-Solomon decoders. It was designed particularly for near-earth space missions, but the excellent error correction performance makes it the ideal fit for additional high-throughput applications such as microwave or optical links.

The new CCSDS LDPC IP cores are low-power and low-complexity designs. The decoder has a layered architecture that allows for twice as fast convergence behavior and half the latency when compared to state-of-the-art solutions. Decoder and encoder perform with 1.6 Gbit/s coded throughput when operating at 200 MHz. Decoding latency is 4.3 µs while the encoding latency is only 40 ns.

The LDPC decoding algorithm gains more than 2.5 dB against Reed-Solomon-based solutions of the same code rate. This gain allows for more reliable data transmission, less power consumption or for an increased transmission range.

The IP cores are available for ASIC and FPGA (Xilinx and Altera) technologies either as source code or encrypted source code. In addition, the cores come with HDL simulation models, VHDL or SystemC testbench, bit accurate Matlab, C or C++ simulation model and comprehensive documentation.

For more information, please visit the product page or contact us.

About Creonic

Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for communications systems design and for complex signal processing functions such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. Creonic’s product portfolio covers standards that include DVB-S2X, DVB-RCS2, WiFi, WiGig, and UWB. These cores are applicable for ASIC and FPGA designs. For more information, please visit www.creonic.com.

Contact

Senay Unal

Manager, Marketing and Sales

Email Contact

+49 631 3435 9886



Read the complete story ...
Featured Video
Jobs
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise