Powerful New Capabilities Featured
AUSTIN, Texas — (BUSINESS WIRE) — January 29, 2015 — Today the Silicon Integration Initiative (Si2) announced release of the Common Power Format (CPF) Version 2.1, incorporating major enhancements to the widely adopted low-power intent format. CPF 2.1 has been approved as an Si2 standard by the Low Power Coalition (LPC).
The enhancements and new capabilities in CPF 2.1 consist of four major categories:
1. Introduction of a “Preserved” hierarchical boundary: In many hierarchical design flows it is critical that the design's power intent is implemented exactly the same for each instance of a design regardless of whether this design is evaluated within a higher level bock or standalone.
CPF 2.1 allows the specification of a “preserve power model” which specifies that the design/instance will be implemented independent of its LP design context. This style of model is used for a variety of hierarchical design flows. The preserve boundary provides a mechanism where the power intent of a design can be used to implement the design in isolation and still be easily integrated into upper level design and verification flows.
2. Expanded Capabilities for Defining Boundary Ports: Boundary ports provide a mechanism to communicate requirements and design details on an IP boundary. CPF 2.1 expands the CPF 2.0 definition of boundary ports to provide additional detail and flexibility.
3. Supply Resolution: Supply resolution is a new concept for CPF 2.1. It defines the behavior for complex power supply networks where a supply net (power/ground net) of a domain is multiple driven. The user can specify if the multiple drivers should be treated as “onehot” or parallel. Static verification and simulation tools can then correctly model the behavior of multiple drivers. Based on these equations, the tool can derive the necessary shutoff conditions and active state conditions.
4. Ability to specify allowed/disallowed domains for global cells: CPF 2.1 adds the ability to specify the allowed set of domains that can power any global cells inserted in a power domain. Due to physical design considerations, not all power supplies are available in all areas of the chip. The new features specify exactly which domains area allowed or not allowed for global cell insertion. These options ensure a consistent power association for all tools in the design flow.
CPF 2.1 is available for download at: http://www.si2.org/?page=811
On January 29th, at the DesignCon Conference in Santa Clara, there will be a panel entitled, “System-Level Power Modeling—What’s the Big Deal?”, where leading industry experts from AMD, Avago Technologies, Cadence, Docea Power, Qualcomm, and Si2 will focus on the growing need to take a higher level and more flexible approach in modeling and simulating power concerns in design. The panelists will explore some of the most critical questions facing designers today, including best practices, current limitations, and future trends in system level power modeling. This panel is sponsored by Si2’s Low Power Coalition (LPC). Click here for details: http://www.designcon.com/santaclara/scheduler/session/system-level-power-modeling-whats-the-big-deal
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: ANSYS (NASDAQ: ANSS), ARM (Nasdaq: ARMHY), Atrenta, Cadence Design Systems (Nasdaq: CDNS), Doecea Power, Entasys, IBM (NYSE: IBM), Avago (formerly LSI - Nasdaq: AVGO), and STMicroelectronics (NYSE: STM)
About Si2
Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 27th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. www.si2.org
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Contact:
Silicon Integration Initiative (Si2)
Bill Bayer, 512-342-2244 ext.
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