Si2 to Sponsor “3D Architectures for Semiconductor Integration and Packaging Conference”

Si2 Keynote Address Will Focus on a 3D Design Ecosystem for IoT

AUSTIN, Texas — (BUSINESS WIRE) — October 22, 2014 — Silicon Integration Initiative (Si2) announced today its sponsorship of the 3D Architectures for Semiconductor Integration and Packaging Conference (3D ASIP). This conference will be held December 10-12, 2014, at the Hyatt Regency San Francisco Airport, Burlingame, California, and is organized by RTI International. Steve Schulz, President and CEO of Si2, will deliver one of the keynote addresses, “A Design Ecosystem for Internet of Things, How 3D IC Standards will Enable a New Growth Paradigm.”

“Although 3D integrated circuits (3DICs) have long been anticipated as the major emerging alternative to classical process scaling, the coming wave of devices driving the Internet of Things (IoT) era will mandate a new set of integration requirements that only 3DICs can properly satisfy,” said Steve Schulz, President and CEO of Si2. “The need to integrate a wide range of functionality - spanning digital, memory, analog, RF, MEMS, sensors, and energy harvesters - cannot be economically addressed exclusively with single-die solutions. Yet the challenges also extend into new design methodologies supporting extreme low power operation, custom packaging co-design and optimization, and including system-level interfaces with embedded software and big data analytics. By analyzing the characteristics of upcoming growth market categories from the system level, we can assess the changing design methodologies required and, from that, infer the new types of design data exchanges needed to support cost-effective design involving 3DICs.”

Si2’s members have been supporting a range of new 3D design flow standards under the Open3D Technical Advisory Board. These include the already-released Chip-Package Interface Protocol standard supporting multi-die power distribution networks, a Design Exchange Format for Thermal Management, and a Pathfinding specification for 3D design optimization. An industry survey of priorities is being developed to guide the next phase of standards development to enable an efficient 3DIC design ecosystem.

Now celebrating its 11th year, the longest running conference series on this topic – 3D ASIP – continues to be an outstanding venue to meet with leaders from around the world to learn and discuss the latest technology and market insights into 2.5/3D device and systems integration and packaging. The conference format offers attendees a platform to gain the latest information from invited speakers on technology progress and industry trends that define this sector today and tomorrow. Along with the invited presentations, the full program includes two preconference symposiums, and various networking functions with opportunities to meet and talk with fellow industry leaders.

Registration and additional information is available at: www.3dasip.org.

About the Open3D TAB

The Open3D TAB is chartered to define open standards for design data formats and interfaces to enable interoperable 2.5D and 3D design flows and co-design Member companies are: Altera (NASDAQ: ALTR), AMD (NYSE: AMD), ANSYS (NASDAQ: ANSS), Atrenta, Cadence Design Systems (NASDAQ: CDNS), Fraunhofer Institute, GLOBALFOUNDRIES, Helic S.A., IBM (NYSE: IBM), Intel (NASDAQ: INTC), Invarian, Mentor Graphics (NASDAQ: MENT), Qualcomm (NASDAQ: QCOM), R3Logic, SEMATECH, STMicroelectronics (NYSE: STM), and Texas Instruments (NYSE: TXN).

About Si2

Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards and shared R&D collaboration to improve the way integrated circuits are designed and manufactured. Now in its 26th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org.



Contact:

Silicon Integration Initiative
William Bayer, 512-342-2244, ext. 304

Featured Video
Jobs
GPU Design Verification Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise