For detailed information about all Synopsys activities at ITC, including the Test SIG event, please visit: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/itc-2014.aspx.
To register for the Test SIG event, please visit: http://www.synopsys.com/cgi-bin/testsig14/reg1.cgi.
What: Test SIG 2014 Event
Topic: The latest silicon test technologies
When: Monday, 10/20, 6:30 p.m. – 9:30 p.m.
Where: ITC 2014, Metropolitan Ballroom, Sheraton Seattle Hotel, Seattle, Washington
Description: Test experts from leading semiconductor companies and foundries will discuss the latest in silicon test technologies and share their experiences and insights on how to achieve higher test quality and lower test cost, faster. Topics to be discussed include: new fault models for emerging process nodes and FinFETs, new compression technologies, latest diagnostic techniques and advanced memory test and repair.
Dr. de Geus will welcome attendees, experts will present, and a question and answer session will follow each presentation for direct speaker-audience interaction. During this dinner event, attendees will have the opportunity to talk with industry peers and the Synopsys test research and development staff. This event is open to all IC designers, managers and members of the media interested in increasing test quality and reducing test cost.
Synopsys Exhibit (Booth #511)
Tuesday, 10/21, 10:30 a.m. – 5:30 p.m.
Wednesday, 10/22, 9:30 a.m. – 5:00 p.m.
Thursday, 10/23, 9:30 a.m. – 1:00 p.m.
Come learn about the latest innovations in Synopsys' test solution for achieving higher defect coverage, higher compression, faster yield learning and improved life-cycle reliability.
Opening Plenary Keynote: Testing Positive… for Complexity
Tuesday, 10/21, 9:00 a.m. – 10:30 a.m.
Dr. Aart de Geus, chairman and co-CEO, Synopsys
Multiple Paper Presentations and Panels
Synopsys test experts will participate in a number of technical sessions, panels and workshops within the ITC 2014 program. These activities will cover a broad array of test-related topics, with a particular focus on achieving higher defect overage, compression and life-cycle reliability.
For a comprehensive list of Synopsys activities at ITC, please visit: http://www.synopsys.com/Tools/Implementation/RTLSynthesis/Test/Pages/itc-2014.aspx
ABOUT THE SYNOPSYS SYNTHESIS-BASED TEST SOLUTION
The Synopsys synthesis-based test solution is comprised of DFTMAX™ Ultra, DFTMAX and TetraMAX for power-aware logic test and physical diagnostics; the DesignWare® STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System® for embedded test, repair and diagnostics; Yield Explorer® tool for design-centric yield analysis; and the Camelot™ software system for CAD navigation. Synopsys' test solution combines Design Compiler RTL synthesis with embedded test technology to optimize timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results due to zero or minimal design iterations. The solution contains value links among the test products and across the Synopsys Galaxy Design Platform to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.
ABOUT SYNOPSYS
Synopsys, Inc. (Nasdaq: SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at www.synopsys.com.
EDITORIAL CONTACTS:
Sheryl Gulizia
Synopsys, Inc.
1-650-584-8635
Email Contact
Lisa Gillette-Martin
MCA, Inc.
1-650-968-8900, ext. 115
Email Contact
SOURCE Synopsys, Inc.
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