Cadence and ARM Expand Collaboration for 64-bit Processor Designs

SAN JOSE, Calif., 20 May 2014

Highlights:
  • EDA Technology Access Agreement gives Cadence access to ARMv7 and ARMv8-A architecture-based processor IP, ARM® Mali™ GPUs, System IP and physical libraries to enable tools optimized for these IPs and the development of designs achieving the required power, performance and area (PPA)
  • First such agreement for ARM’s 64-bit v8 architecture, which includes the ARM Cortex®-A50 processor series
  • Tighter integration of Cadence tools with ARM technology for easier SoC design, verification and implementation, helping to shorten the time to market.
Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced the signing of the first EDA (Electronic Design Automation) Technology Access Agreement with ARM Holdings plc [(LSI: ARM), (NASDAQ: ARMH) that includes access to the ARM v8-A 64-bit architecture in the ARM Cortex-A50 processor series. This agreement also provides access to ARMv7 32-bit processor technology, ARM Mali GPUs (graphic processor units), System IP and ARM Artisan® libraries. This collaboration further enables ARM and Cadence® to provide world-class technology for energy efficient and high performance applications for mobile, consumer, networking, storage, automotive and other end market products.

The ARMv8-A architecture, with its 64-bit support, enables ARM processors to become more broadly deployed in server and desktop applications as well as the migration of 64-bit operating systems to mobile applications. Find out more about the Cortex-A50 processor series at http://www.arm.com/products/processors/cortex-a50/index.php.

“We are dedicated to empowering developers, designers and engineers to innovate around ARM technology and ensuring a fast, reliable route to market,” said Pete Hutton, executive vice president and president of product groups, ARM. “The co-optimized tools, IP and physical libraries resulting from this agreement will accelerate the deployment of ARM’s most advanced technologies. We expect that this will be a huge boost to developers of mobile devices, servers and the exploding market for Internet of Things.”

Key features of the agreement:
  • Expands Cadence’s ARM-based solution to provide 64-bit SoC optimized tools and flows. With access to this ARM IP, Cadence can tune performance, enhance debug and deliver a more streamlined process to enable shorter ARM-based system development.
  • Augments ARM-based RTL-to-GDSII design, implementation and signoff flow to deliver optimum power, performance and area.
  • Broadens existing ARM-based System Verification solution to expand design, integration, and hardware/software verification environment for cache coherent multi-core 64-bit designs.
  • Automated creation of verification environments and performance analysis for ARM System IP allows designers to adopt and verify earlier and with more confidence.
  • Provides training for mutual customers on the use of Cadence tools with ARM technology.
“Cadence becoming the first EDA partner to access ARMv8-A deepens our collaborative customer enablement, flow optimizations and development and deployment of ARM processor IP centric automation technologies” said Charlie Huang, senior vice president, Worldwide Field Operations and System & Verification Group at Cadence. “Jointly we can provide better system design enablement, meeting our mutual customers’ time-to-market needs for power-efficient 64-bit market-leading products.”

About Cadence

Cadence Design Systems (NASDAQ: CDNS) plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
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