Will Demonstrate SystemVerilog, VHDL Parsers with Easy-to-Use C++, Perl APIs

ALAMEDA, CALIF., May 22, 2013 -- WHO: Verific Design Automation ( www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers

WHAT: Invites attendees, especially computer-aided design (CAD) managers and system-on-chip (SoC) designers, to Booth #2141 during the 50th Design Automation Conference (DAC). They will learn how they can build their own one-of-a-kind EDA tools with industry-standard SystemVerilog or VHDL front-ends from Verific, using C++ or Perl application program interfaces (APIs).

WHEN: Monday, June 3, through Wednesday, June 5, from 9 a.m. until 6 p.m. daily

WHERE: Austin Convention Center, Austin, Texas. Look for the giraffe to locate the Verific Booth #2141.

Twenty-fiveother DAC exhibitors selected Verific’s parsers and elaborators to serve as their SystemVerilog, Verilog, VHDL and UPF software to serve as the front end for their EDA and FPGA analysis, simulation, verification, synthesis, emulation and test tools.

For more information about Verific, go to: www.verific.com.

The entire 50th DAC program can be found at: www.dac.com.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif.  94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website:  www.verific.com. Follow Verific on Facebook: http://www.facebook.com/pages/Verific-Design-Automation/100448363329771.


Contact:

Nanette Collins,
Public Relations for Verific,
Tel.:(617) 437-1822
Email Contact