Verific Design Automation Increases Revenue by 20% in 2012

Reputation for Quality and Reliable Software, Exceptional Customer Service Drive Success

ALAMEDA, CALIF. – January 28, 2013 – Verific Design Automation ( www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.

"Much of our business in 2012 came as a result of our reputation for quality parsers, reliable software, and excellent customer service, the hallmarks of our corporate culture," says Michiel Ligthart, Verific's president and chief operating officer. "EDA developers continue to select our parsers so that they can focus on their core competencies and get their products to market more efficiently."

In 2012, Verific signed six new licensed customers in a mix that includes both electronic design automation (EDA) companies and integrated device manufacturers (IDMs). Several existing customers added further software to their existing product mix.

Verific's software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.    

Featured Video
Latest Blog Posts
Sanjay GangalThe Dominion of Design
by Sanjay Gangal
EDACafe Predictions 2025 – SiFive
Sanjay GangalEDACafe Editorial
by Sanjay Gangal
Industry Predictions for 2025 – Cofactr
Sanjay GangalEDACafe Editorial
by Sanjay Gangal
EDACafe Industry Predictions for 2025 – Everspin
Jobs
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
CHIPLET SUMMIT 2025 at Santa Clara Convention Center Santa Clara CA - Jan 21 - 23, 2025
ESD Alliance "Savage on Security” Webinar at United States - Jan 23, 2025
SEMICON Korea 2025 at Hall A, B, C, D, E, GrandBallroom, PLATZ, COEX, Seoul Korea (South) - Feb 19 - 21, 2025
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2025 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise