eSilicon Engineers' Comprehensive Book on Low-Power Design for ASICs Is Now Available

SUNNYVALE, CA -- (Marketwire) -- Feb 05, 2013 -- eSilicon Corporation, the largest independent semiconductor design and manufacturing services provider, today announced that An ASIC Low-Power Primer is now available from Springer, a leading publisher of science and technology reference books. Written by eSilicon engineers Dr. J. Bhasker, architect, and Dr. Rakesh Chadha, director of design technology, the book provides an invaluable primer on the techniques utilized in the design of low-power digital semiconductor devices.

"System power management is a critical aspect of IC design -- everyone cares about low-power design in order to be green; it is no longer the domain of mobile applications. Power management spans technology, standard cell library and memory selection, IP design, RTL design and physical implementation," said Dr. Prasad Subramaniam, eSilicon's vice president of design technology. "This book covers all these topics. And it would be difficult to find a better source than eSilicon and Rakesh and Bhasker who have extensive experience with power management and low-power IC design over multiple generations of technologies. This book reflects the expertise and experience of two of our finest engineering team members and demonstrates the quality of talent we apply to customers' projects every day."

The authors guide readers through architectural and implementation techniques, system power consumption analysis, low power design techniques and more. The duo also wrote Static Timing Analysis for Nanometer Designs: A Practical Approach.

About the Authors
J. Bhasker is an expert in the area of hardware description languages and RTL synthesis. Prior to joining eSilicon, he was a distinguished member of the technical staff at Bell Laboratories. He has published a number of books and papers, primarily in the area of design automation and high-level synthesis algorithms. He was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He holds a Ph.D. in Computer Science from the University of Minnesota.

Rakesh Chadha is an ASIC design specialist with over 25 years of experience in timing and signal integrity at Bell Laboratories, Cadence and eSilicon. He was responsible for the timing and signal integrity for the Sematech project on Chip Parasitic Extraction and Signal Integrity Verification. He has been responsible for complex SOC design methodology for several generations of process technologies. He holds a Ph.D. in Electrical Engineering from the Indian Institute of Technology Kanpur.

About eSilicon
eSilicon, the largest independent semiconductor design and manufacturing services provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk path to volume production. eSilicon serves a wide variety of markets including the communications, computer, consumer and industrial segments. www.esilicon.com.

eSilicon -- Enabling Your Silicon Success™

eSilicon is a registered trademark, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

Contacts: 
Sally Slemons 
eSilicon Corporation 
408-616-4695 

Email Contact 

Susan Cain
Cain Communications
503-538-2747

Email Contact 


Featured Video
Jobs
CAD Engineer for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise