Contact: Jasper Design Automation – DAC Booth #830 Rob van Blommestein
650-966-0234 p
Email Contact
MOUNTAIN VIEW, Calif. – May 23, 2012 – Jasper Design Automation, the leading provider of verification solutions based on formal technology, will be partnering with several of its customers to present a series of verification seminars at its booth #830 at the Design Automation Conference (DAC), June 3-7 in San Francisco. Representatives from ST Microelectronics, ARM, Broadcom, and Nvidia will each discuss how they addressed a specific verification challenge with Jasper solutions. The presentations will be repeated each day. Abstracts and times of each presentation are included below.
ST: Low Power Verification and Optimization with Jasper Formal
ST Microelectronics will discuss the verification challenges associated with sophisticated low-power designs, and ways those challenges are being addressed by Jasper's power-aware formal verification technology.
Monday, June 4, 1:00 PM
Tuesday, June 5, 9:30 AM
Wednesday, June 6, 1:00 PM
ARM: Multi-processor Verification Success with Jasper Formal - The Proof Is in the ROI
In this seminar, ARM will discuss how Jasper's advanced formal technology helped to verify a variety of issues that significantly improved time-to-market. Details will be given on how Jasper was integrated into ARM's overall verification flow so that bugs found using Jasper formal could be tracked and the ROI measured. Examples will be shown on how Jasper formal technology was used to find more bugs in less time and provide more stabilization in the verification effort. The seminar will also explore how Jasper is partnering with ARM to utilize formal technology on future projects for mitigating design and verification risks.
Monday, June 4, 4:00 PM
Tuesday, June 5, 2:00 PM
Broadcom: Clock Sensitive FIFO Verification with JasperGold Apps
Broadcom will discuss the challenges associated with clock-sensitive FIFO verification through the exploration of two different case studies – Elastic FIFO, designed to handle read/write clock frequency differences, and Phase Compensation FIFO, designed to handle read/write clock phase differences. The use of simulation alone was not enough to thoroughly verify Broadcom's designs. To mitigate design and verification risk, Broadcom employed Jasper technology.
Monday, June 4 at 2:30 PM
Nvidia: Sequential Equivalency Checking for Power Optimization
Nvidia faces critical verification challenges involving designs such as a GPU Streaming Multiprocessor, SIMD processor and a complex instruction set for graphics and compute. Among the verification challenges that Nvidia must overcome is sequential equivalence checking. This two-part seminar will begin with Nvidia discussing their methodology for sequential equivalence checking of two RTL models. Examples of how JasperGold was used to verify the correctness of clock gating optimization will be shown, as well as the results of how this methodology enabled higher verification coverage and identification of bugs not found with dynamic methods. The second half of the seminar will focus on the use of Jasper's prototype JasperGold App for sequential equivalence checking on one of Nvidia's most complex blocks. A roadmap for the availability of the JasperGold Sequential Equivalence Checking App will be shared.
Monday, June 4, 11:00 AM
Tuesday June 5, 4:00 PM
Wednesday, June 6, 11:00 AM
Jasper: Achieving Coverage Closure with Jasper Formal
In this seminar, Jasper representatives will cover various coverage metrics for formal verification and provide a recommended methodology towards how formal verification technology and the associated metrics that can be leveraged to accelerate the overall coverage closure process.
Wednesday, June 6, 10:00 AM
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics. Jasper technology has been an integral part of over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity; and accelerate time to market.
Jasper Design Automation and the Jasper Design Automation logo are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.
