HENDERSON, Nev. — (BUSINESS WIRE) — May 23, 2012 — Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, will bring its top engineers to meet one-on-one with attendees at the industry’s annual Design Automation Conference ( DAC). This year, DAC runs June 3-7, 2012 at the Moscone Center in San Francisco, California.
Aldec offers convenient pre-registration for Technical Sessions: http://www.aldec.com/DAC2012. Registrations confirmed to date indicate the top trending Aldec sessions at DAC are:
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Simulation on the Cloud: Unlimited Possibilities |
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| Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers. | |||||
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UVM in Aldec Tools: Verification and Debugging |
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| Aldec’s support of the latest UVM library, graphical debugging features to help designers find and fix issues more efficiently, and exciting future enhancements coming later this year. | |||||
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High-Level VHDL Verification Doing Well with Help of New OS-VVM Community |
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| Aldec, an early OS-VVM supporter, is hosting an open OS-VVM User Group Meeting on Monday, June 4, 2012 at 2:00pm in Booth #2126. | |||||
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Emulation |
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Achieve 10+ MHz Emulation of 100 Million ASIC Gates with True RTL Debugging ; Hardware and Software design teams can also now Use Virtual Platforms with Transaction Level Emulation . |
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Other popular Aldec sessions include: |
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Requirements-based FPGA Testing Method for DO-254 |
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Early Validation of Custom IP for Zynq-based Designs |
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Interoperable IP Encryption (P1735): Safe and Smooth Multi-vendor Encryption Flow |
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A Highly Productive, Integrated Analog Mixed-Signal (A/MS) Solution from Tanner EDA |
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Ask Aldec (Questions, Updates, Roadmaps) |
