Cadence Seminar: Reduce SoC Development Time with Cadence IP and VIP (May 22 in Boston and May 24 in Ottawa)


 
     
 

How to Choose Design IP and Verification IP to Reduce SoC Development Risk

Speed IP integration, improve SoC quality, and reduce schedule risk with proven design IP and verification IP (VIP) in this free half-day seminar from Cadence - coming to your area soon.

SoC project managers need production-proven design IP that meets the unique criteria of each SoC project.   Power, performance, and area are always key requirements, but other more subtle aspects to IP selection may not be as evident.  Learn how to distinguish between good, better and best in class IP for memory and interface IP including DDR3/4, Flash, PCIe Gen3, NVM Express and high-performance, low-jitter SerDes. 

Verification teams need proven and technically advanced verification IP that helps find design bugs quickly and efficiently.  Learn why over 500 customers have used Cadence VIP on thousands of projects to verify more than 40 protocols including the newest and most complex such as AMBA 4 ACE, PCI Express Gen 3, USB 3.0, MIPI LLI, DDR4, and NVM Express.

Space is limited.  Register by sending an email to  Email Contact

What you’ll learn:

  • Design IP Topics
    • How an optimized soft IP configuration reduces area and power
    • How to save time and money implementing NVM Express
    • High-performance SerDes– it’s not just throughput that’s important
    • Highly configurable early access to new standards accelerates design time
  • Verification IP Topics
    • Don’t just collect coverage, verify specification compliance
    • Ensure cache-coherency in multi-core ARM SoCs
    • Confirm single-root and multi-root I/O virtualization for PCI Express Gen 3
    • Special considerations for verifying the new MIPI Low Latency Interface (LLI)
    • How to verify stacked protocols like NVM Express

Seminar Locations:

Boston

Tuesday, May 22nd

Courtyard Boston Marlborough

75 Felton Street, Marlborough MA

1-508-480-0015 (for directions only)

Ottawa

Thursday, May 24th

Brookstreet Hotel

525 Legget Drive, Ottawa Ontario

1-613-271-1800 (for directions only)

 

Agenda:

  • Registration & continental breakfast begin at 8:30 am
  • Seminar: 9:00 am – 2:00 pm (lunch provided)

 

Space is limited.  Register by sending an email to  Email Contact

 
 
© 2012 Cadence Design Systems, Inc. All rights reserved.  
 



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise