EdXact Demonstrates New Parasitics Analysis Solution Viso at CDNLIVE Silicon Valley

Viso allows for detailed interconnect analysis and debug

Santa Clara, CA and Grenoble, France

Backend verification specialist EdXact SA today announces the availability of Viso™, the companies solution for parasitics analysis. Viso allows designers to carry out parasitics oriented static analyses of designs of any size. The tool is intended to be used for those increasing number of cases, where interconnect related problems turn debug difficult, where there is a need for detailed analysis and where spice simulation, even accelerated, cannot satisfy the tight time constraints of a design and verification team. The tool has been released at the end of 2011 and has been adopted at several leading edge semiconductor companies.

Typical applications of the tool comprise today the analysis of ESD related electrical layout rules, simulation pre-qualification in order to avoid unnecessary spice simulations, verification of electro-migration related design rules, detection of opens and shorts, sufficient via connections, and the validation of the layout of Power MOS transistors.  Viso is integrated into EdXact's Parasitics Analysis Platform Alps™. The platform has been designed with the observation, that layout parasitics need dedicated and smart analysis at advanced design nodes. The underlying mathematical database allows for very fast and accurate analyses.

Jivaro™, EdXact's netlist reduction engine, has been tightly integrated into Alps and has received a very tight link into Cadence's design framework. This link allows designers to generate extracted views for designs that are generally too big to deal with natively.

About CDNLIVE

CDNLIVE is a user conference, organized by Cadence Design Systems. It is being held March 13-14, 2012 at DoubleTree Hotel in San Jose, California.

About EdXact

Founded in 2004, EdXact SA focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with sales offices in Japan, Korea and Taiwan. For additional information: http://www.edxact.com

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