Grenoble, France, November 3rd -- DeFacTo Technologies SA today announced the STAR Toolbox for RTL design and verification engineers. Through a Tcl API and based on an RTL-to-RTL editing and verification platform, STAR provides multiple tools to help designers solve key design verification and implementation tasks before logic synthesis:
- STAR – Ck : Structural clock verification fully at RTL between source and destination clocks with test benches generation and graphical debug capabilities
- STAR – Power: RTL structural power verification and DRCs with automatic insertion of low power structures (isolation cells, level shifters, …)
- STAR – Eco: Gate-level and RTL Engineering Change Order with automated generation of both gate-level and RTL.
By enabling designers to perform critical design and verification tasks at RTL, STAR tools deliver significant time savings and quality improvements. “DeFacTo has been traditionally offering EDA tools to solve Design-for-Test problems. With the STAR toolbox, we are extending our product portfolio and helping designers and verification engineers to solve challenging design and verification problems as early as at RTL. Compared to traditional EDA or in-house tools, first customer validations of the STAR Toolbox on real chips is highly promising in terms of ease of use, shortening TAT and interoperability with mainstream design and verification flows”, said Chouki Aktouf, CEO of DeFacTo Technologies.
For additional information about the STAR Toolbox, please refer the DeFacTo website: www.defactotech.com.
About DeFacTo Technologies
DeFacTo solutions enable designers to achieve “Design & DFT” closure at RTL by delivering a high quality suite of tools which cover IP integration, design verification and DFT Signoff needs. DeFacTo is headquartered at 167 rue de Mayoussard, 38430 Moirans, France. For more information, visit us at www.defactotech.com.
