Cadence Library Characterization Scripts Now Available in New TSMC Reference Kit

SAN JOSE, CA -- (MARKET WIRE) -- Oct 17, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has collaborated with TSMC to provide mutual customers access to a library characterization reference kit. The Cadence® Library Characterizer (Altos Liberate) reference kit for TSMC's standard cell libraries is now available to TSMC customers for download on TSMC-Online. The reference kit, along with the Cadence Library Characterizer technology, enable customers to re-characterize their standard cell libraries in-house, on their own schedule with the same characterization technology and setup used internally at TSMC, delivering better consistency.

"Through our work with TSMC on the mission-critical challenge of foundation IP characterization, customers can now leverage the same technology used in-house at TSMC with the same setup and constraints, helping them address the specific design challenges created through changes to their standard cell libraries," said Wilbur Luo, group director, product marketing, Silicon Realization Group at Cadence. "We are always looking for ways to give customers greater control over the design processes, and TSMC's introduction of its Library Characterization Reference Kit does just that."

Shrinking process geometries increase process variations and make creation of accurate noise, power and timing models for foundation IP very complex given smaller time-to-market windows. The combination of TSMC's Library Characterization Reference Kit and the Cadence Library Characterizer allows customers to speed their overall design schedule.

"Enabling our customers to re-characterize their standard cell library IP not only gives them more control over their schedule, it also gives them more control to address the timing, noise and power of their design," said Suk Lee, director of Design Infrastructure Marketing at TSMC. "By providing the Library Characterization Reference Kit online, we are giving our customers the tools needed to assure re-characterization that addresses their specific design challenges."

The Cadence Library Characterizer technology enables re-characterization across process changes and additions to the IP library. It enables ultra-fast and accurate characterization of memory, standard cell libraries and other foundation IP, generating required models for SoC implementation. TSMC has made Cadence Library Characterizer scripts for standard cell libraries available for 40- and 28-nanometer process nodes.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

Email Contact 


Featured Video
Jobs
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
GPU Design Verification Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
Phil Kaufman Award Ceremony and Banquet to be held November 6 at Hayes Mansion at Hayes Mansion 200 Edenvale Ave San Jose CA - Nov 6, 2024
SEMICON Europa 2024 at Messe München München Germany - Nov 12 - 15, 2024
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise