8.30

Arrival: Refreshments and Networking

9.30

Introduction:  Mike Bartley, TVS

9.35

Harry Foster, Mentor Graphics

Presentation on Harry’s annual survey

Title: From Volume to Velocity: The Transforming Landscape in Function Verification

Abstract: There has been a remarkable acceleration in the adoption of advanced verification methodologies, languages and new standards.  This is true across all types of IC design and geographic regions.  Designers and verification engineers are surprisingly open to new approaches to keep pace with the relentless rise in design density.  They are looking beyond simply increasing the volume of verification to instead using advanced techniques to improve the velocity of verification.

The result is design teams have not lost ground on meeting schedule goals or first-pass silicon success even as design complexity has grown.  Now the focus is shifting to appreciably improving those metrics while shrinking verification costs. 

This keynote discusses the state of functional verification past, present and future.  Data from the recent 2010/11 Wilson Research Group Functional Verification Study (the world’s largest industry functional verification study ever conducted) will be presented, and insights into emerging challenges and solutions will be discussed.

Biography:  Harry Foster is Chief Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored six books on verification--including the 2008 Springer book Creating Assertion-Based IP.  Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

10.20

Panel Session:  Our Top Verification Challenges

A view on the verification challenges from some major semi-conductor companies around Europe

Bryan Dickman, ARM (Director Design Assurance, Processor Division)

Biography: Biography: Bryan has been working within CPU Verification at ARM since 1996, holding several different posts including Engineering Manager for the Cambridge CPU team around the time of the ARM11 development program. Currently program managing the Viper program which is an ongoing program to further extend and refine ARM’s design verification capabilities.  Bryan gained a BSc in Physics from Leeds University in 1983, and has previously worked for Ferranti and ICL in the UK as a hardware design engineer.

Olivier Haller, STMicroelectronics

Biography : Olivier Haller is Verification Methodology Manager in the Functional Verification Group at STMicroelectronics.  He is responsible for the definition and deployment of verification solutions at ST, including support for key ST and ST-Ericsson projects.  Oliver started his career at ST in 1998 as digital designer for wireless products.  In 2000 he pursued functional verification as member of the CAD support team, introducing coverage-driven verification techniques.  Since 2004 he is leading the design verification solutions team in ST’s central verification group where he has been pioneering the introduction of functional qualification within ST to qualify IPs and SOCs, applying business intelligence techniques to verification, introduced SOC level test generation and proposed other innovative solutions to improve quality of verification environments and increase productivity of verification engineers across the company.  Oliver graduated from Grandes Ecoles d ingénieur en électronique in Grenoble and holds a joint ENSERG/ENSIMAG engineering degree in electronics and computer science.

Plus others

11.00

Refreshments and Networking

11.30

Mike Stellfox, Cadence Design Systems

Title: TBD

Abstract:  The main focus on advancing verification in the industry for the past few years has been centered more on IP verification.  This includes constrained-random, coverage and metric driven verification based on the UVM e or SystemVerilog methodology.  While these approaches are certainly needed for bottoms-up IP to Subsystem verification, they run out of steam when you consider the verification challenges for large-scale multi-core SoCs.  In fact, there is a rather large gap in how most SoCs are verified today relevant to what is needed in order to have a scalable and efficient SoC development process.  The current generation of SoCs being developed by many customers present significant challenges in how to efficiently verify the large integration of digital and analog IPs along with a growing amount of SW content and increasingly more sophisticated low-power design features.  This presentation will review these challenges and outline some directions where new solutions are required to address the significant verification gaps which exist today for efficient SoC Realization.

Biography:  Mike Stellfox leads the SoC and System Verification Solutions Architecture Team, whose primary charter is to understand customer verification challenges in order to develop verification methodology and drive requirements for the development of the Cadence SoC Verification Solutions.  These methodology-based solutions include verification planning and management, OVM/UVM e, SystemVerilog testbenches, Debug, Metric Driven Verification, and HW/SW Verification.  Mike has been working to advance the field of functional verification for the past 15+ years in various roles from Verisity Verification Consulting Engineer, to leading the Verisity Field Organization, to developing verification methodology and solutions.  Mike began his career at IBM, where he worked as an ASIC Designer responsible for designing and verifying a variety of 2D and 3D graphics chips. 

12.00

Serrie Chapman and Darren Galpin, Infineon Technologies

Title:  The drive for Requirements Engineering and how it may affect verification

Abstract :  Currently there is a strong drive towards improving traceability between stakeholders, internal and external, and the implemented hardware.  The main obvious benefits are driving quality through ensuring completeness and giving visibility to over and under-engineering.  However it is also identifying holes within the traceability flow that require new solutions such as how we ‘prove’ requirements.  It is also driving a change in how we document,  the current push is towards using UML to write the top level requirements however there is no reason why this may not in future be driven further down the chain to testplans and testbench documentation.  With that in mind we would like to take it into consideration before standards start to dictate it, is it usable and what could the benefits be.

Biography : Darren Galpin started his career with STMicroelectronics in 1997 in Product Engineering, switching to verification in 1999.  He joined Infineon in 2000 having worked on both TriCore processor verification, SoC verification and IP verification and became System & IP Verification Manager in November 2009.  Darren became the IEEE-1647 Vice-Chair in 2007 and Chair in November 2009.

Biography : Serrie Chapman  started her career in semiconductors with Infineon in 2000 after a career change.  Serrie has worked on TriCore processor, SOC and a variety of IP verification projects.  Serrie moved over to full-time Requirements engineering after having experimented and worked in the background on a variety of requirements traceability and completeness projects since 2004.  Serrie is also a member of the IEEE-1647 and was previously secretary on the Working Group for several years. 

12.20

Mike Benjamin, TVS

Title:  Benchmarking Functional Verification

Abstract:  We are all aware of the need for constant improvement to meet the ever growing challenges posed by functional verification.  However when it comes to measuring how our verification processes meet these challenges we quickly discover that getting to grips with benchmarking is actually incredibly difficulty.

Most common benchmarking models, such as CMMI, attempt to be too general. They end up being far too complex and costly to easily apply to real projects, and their results are often too far removed from specific actions. This talk describes how a benchmarking process can overcome these limitations and become a practical tool for driving improvements in your verification processes. Firstly a verification specific methodology eliminates all the generalisations that normally make it so hard to relate benchmarking to real life issues.  Secondly incorporating a simple process for linking required capabilities to actual project practices it becomes possible to quickly identify the most important issues.  This structure can easily be customised to the specific needs of different application domains, different design styles or different companies and hence be kept relevant whatever the project.

The talk concludes by describing how benchmarking results are validated and then used for planning verification process improvements.

Biography:   Mike has an MA in Electrical Sciences from Cambridge, an MSc in Computation from Oxford and over 25 years of industrial experience; mostly working on the verification of leading edge CPUs and SoCs.  For almost 10 years he managed the central verification group at STMicroelectronics, responsible for driving advanced verification methodology and central services such as emulation and formal methods.  These days Mike provides hardware verification consultancy and management services for TVS clients.

12.40

Steve Holloway, Dialog Semiconductor

“Adopting a Methodology”  How and why?  

Title: TBD

Abstract: TBD

Biography:   TBD

13.00

Lunch and Networking  

14.00

Lawrence Loh, Jasper

Formal Verification

Title:   SOC-level Formal Verification

Abstract:  The value of model checking in block and IP level verification has been well-understood in the industry. However, its value in system-level verification has been very limited. System-level verification challenges have been very prominent in recent years as many chips are now SOCs containing a large number of IPs. Jasper has been successfully helping customers by applying model checking in various system-level verification challenges beyond IP interface certification and IP level verification. In this presentation, I want to share some of the system-level applications successes in areas such as system architecture verification, system integration, and system-level debug.

Biography:  

Lawrence Loh, Vice President of Worldwide Applications Engineering, Jasper Design Automation holds overall management responsibility for applications engineering and methodology development At Jasper Design Automation. He has been with the company since 2002. He holds four U.S. patents on formal technologies. His prior experience includes verification and emulation engineering for MIPS,  verification manager for Infineon’s LAN Business Unit, and Digital hardware design for Hughes Network Systems. Lawrence holds a BSEE from California Polytechnic State University and an MSEE from San Diego State.

14.30

Nick Gatherer, ARM

ESL

Title : Does ESL Have a Role in Verification ?

Abstract: Recent years have brought some impressive steps forward in verification methodologies and tools, and yet still we face significant challenges. The relentless growth in system and SoC complexity, including rapidly escalating software content and increasingly sophisticated approaches to multi-core and power management, demand a portfolio of powerful and coherent verification approaches. This presentation will take a holistic perspective on the verification landscape, and highlight some specific domains in which ESL solutions are already contributing to increased verification productivity and confidence.

Biography:   Nick Gatherer is currently Engineering Manager for modelling within the Processor Division of ARM, responsible for the provision of models at multiple levels of abstraction to support both internal development projects and ARM partners. Prior to ARM he also gained extensive experience in the design and management of complex SoC’s, and has lead corporate programs to innovate and exploit advanced technology solutions for verification and system level design. Nick has previously worked for Philips Semiconductors, Cadence, NXP, and Trident Microsystems, and holds an MSc in Microelectronics Systems Design from Brunel University.

15.00

Jean-Marc Forey, SpringSoft

Test Bench Qualification

Title : TBD

Abstract : TBD

Biography:   TBD

15.30

Refreshments and Networking

16.00

Janick Bergeron, Synopsys

Title : TBD

Abstract : TBD

Biography:   TBD

16.30

Panel Session:  The EDA response

17.15

Refreshments and Networking