All Categories : Technical Papers : Case Studies Bookmark and Share

Title : XJTAG cuts PCB debug and test time for nCipher
Company : XJTAG
Date : 25-Sep-2014
Rating :
Downloads : 2

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Boundary scan testing offers a solution to the challenges presented by high component density, the increasing use of area array packages – such as ball grid arrays (BGAs) and Field Programmable Gate Arrays (FPGAs) – and the prevalence of complex, multi-layer PCBs, which make test probe access and bed of nails testing impossible for many new board designs. The XJTAG Development System aims to solve these challenges and also allows test programs to be re-used and optimised for production testing.
User Reviews More Reviews Review This File
Featured Video
Editorial
More Editorial  
Jobs
Sr. Silicon Design Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Upcoming Events
ESD Alliance "Savage on Security” Webinar at United States - Jan 23, 2025
SEMICON Korea 2025 at Hall A, B, C, D, E, GrandBallroom, PLATZ, COEX, Seoul Korea (South) - Feb 19 - 21, 2025
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025
Design, Automation & Test in Europe - DATE 2025 at Palais des congrès de Lyon Lyon France - Mar 31 - 2, 2025



© 2025 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise