All Categories : Technical Papers : White Papers Bookmark and Share

Title : SpyGlass Flow for XILINX FPGA
Company : Synopsys Inc.
Date : 19-Sep-2013
Rating :
Downloads : 577



If download does not start, click here.
Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints.
User Reviews More Reviews Review This File
Featured Video
Jobs
CAD Engineer for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise