SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints.
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