IC designers responsible for the physical implementation of the design face a huge problem of design
sign-off analysis. Today, they need to use different tools to verify the various design aspects, such as
timing, power, voltage drops, and chip temperature. The problem is that each of these analyses needs
the results of all the other analyses. Therefore, typically, these tools are run sequentially in a flow, so
that the results of one tool can feed the next tool.
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