This paper aims at presenting a new model-based flow targeting analog/RF circuits sizing with significant improvements of parametric yield at a
very early stage in the design phase. The flow is then applied on a ST Microelectronics [2] LDO regulator design. In a first step, the regulator is modeled. In the second one, the design is optimally
sized. The process parameters are then modeled, and finally the sensitivity of the design to the process is analyzed.
You are reviewing the
Download.
Your machine is locate at 3.148.108.144.
