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Title : FULLY DIGITAL IMPLEMENTED PHASE LOCKED LOOP
Company : Cologne Chip AG
Date : 26-Feb-2011
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One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated because the usable voltage ranges are decreasing with every new integration step.
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