All Categories : Technical Papers : White Papers Bookmark and Share

Title : Using Formal to Analyze Non-Determinism in Design Reset Schemes
Company : Avery Design Systems, Inc
Date : 12-Mar-2011
Rating :
Downloads : 2

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Reset schemes can be difficult to verify in logic simulation because of the non-determinism caused by unknowns (Xs) in the registers and their inaccurate handling in logic simulation which can mask bugs and potentially lead to failures in silicon. Here, we describe a precise formal approach to X-verification of partial and full reset sequences. Insight, from Avery, addresses two kinds of X issues:
User Reviews More Reviews Review This File
Featured Video
Jobs
Design Verification Engineer for Blockwork IT at Milpitas, California
GPU Design Verification Engineer for AMD at Santa Clara, California
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Sr. Silicon Design Engineer for AMD at Santa Clara, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
Upcoming Events
DVCon Europe 2023 at Holiday Inn Munich – City Centre Munich Germany - Nov 14 - 15, 2024
SEMI MEMS & Imaging Sensors Summit, at International Conference Center Munich Germany - Nov 14, 2024
SEMI | MSIG MEMS & Imaging Sensors Summit at Munich Germany - Nov 14 - 15, 2024
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise