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Title : Using Formal to Analyze Non-Determinism in Design Reset Schemes
Company : Avery Design Systems, Inc
Date : 12-Mar-2011
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Reset schemes can be difficult to verify in logic simulation because of the non-determinism caused by unknowns (Xs) in the registers and their inaccurate handling in logic simulation which can mask bugs and potentially lead to failures in silicon. Here, we describe a precise formal approach to X-verification of partial and full reset sequences. Insight, from Avery, addresses two kinds of X issues:
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