All Categories : Technical Papers : White Papers Bookmark and Share

Title : Solving Verilog "X" issues - a key problem for IP providers
Company : Averant
Date : 11-Mar-2011
Rating :
Downloads : 5

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Paper by Mike Turpin of ARM, Ltd., describing how to use Solidify for Sequential Equivalence check in order to uncover hidden "X" values in a design. This is particularly important for an IP provider where the RTL may be implemented using different synthesis flows. Hidden X's can cause differences between RTL simulation and the actual silicon, which are not caught by design flows that rely on other tools such as Logical Equivalence checking.
User Reviews More Reviews Review This File
Featured Video
Jobs
Senior Firmware Architect - Server Manageability for Nvidia at Santa Clara, California
Design Verification Engineer for Blockwork IT at Milpitas, California
Senior Platform Software Engineer, AI Server - GPU for Nvidia at Santa Clara, California
GPU Design Verification Engineer for AMD at Santa Clara, California
CAD Engineer for Nvidia at Santa Clara, California
Upcoming Events
SEMICON Japan 2024 at Tokyo Big Sight Tokyo Japan - Dec 11 - 13, 2024
PDF Solutions AI Executive Conference at St. Regis Hotel San Francisco - Dec 12, 2024
DVCon U.S. 2025 at United States - Feb 24 - 27, 2025



© 2024 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise