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S13V33_MULTIO_01C
Features

S13V33_MULTIO_05---VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
Features

S13V33_MULTIO_06---VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
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S13V33_MULTIO_DUP_05---VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell
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S13V33_MULTIO_ONFICOMBO_01---VeriSilicon SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO
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S13V33_OSCIO_02---VeriSilicon SMIC 0.13um 1.2V/3.3V OSC IO
Features

S13V33_OSCIO_DUP_02
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S13V33_PCIIO_01
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S13V33_SSTLCOMBO_01
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S13V33_SSTLCOMBO_02---VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
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S13V33_USB11_01_L
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S13V33_USB11_DUP_01---SMIC 0.13um USB 1.1 PHY
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S13V33_VDD33SW_01---SMIC 0.13μm 3.3V Switchable Power Control Block
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SATA Verification IP
Features

SATA-II PHY IP Core
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Serial ATA (SATA) I/II Host Controller - so_ip_sata2_hctrl
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Serial SCSI / SAS Verification IP
Features

SGIO IO T040G-LVCMOS18 CUP, LVCMOS18 ATB CUP 1.8 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
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SGIO IO T040G-LVCMOS25 CUP 2.5 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
Features

SGIO IO T040G-LVCMOS33 CUP, LVCMOS33 ATB CUP 3.3 V Bidirectional LVCMOS with Programmable Schmitt Trigger, Drive & Pull-Up/Down
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SGIO IO T040G-LVDS18 RX CUP, LVDS18 RX TERM CUP 1.8 V, 800 MHz LVDS Reciever With andWithout Input Termination
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SGIO IO T040G-XTAL18 CUP 1.8 V, 40 MHz Crystal Oscillator with Programmable Drive & Limiter Resistor
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SGIO IO T040GP-LVDS18 TX CUP, LVDS18 VREF CUP 1.8 V, 675 MHz LVDS Transmitter
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SGIO IO T065GP-DD2_CUP 1.8 V, DDR2 With andWithout Input Termination
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SGIO IO T065GP-THERMAL DIODE
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SGIO IO T065GP-XTAL33_CUP - 2.5 / 3.3 V, 40 Mhz Crystal Oscillator
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SGIO_IO_T065GP-ANALOG_PADS-Analog I/O Pads with and without ESD Protection
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SGIO_IO_T065GP-LVDS33_RX_CUP - 3.3 V, 750 MHz LVDS Reciever
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SGIO_IO_T065GP-LVDS33_TERM_RX_CUP - 3.3 V, 750 MHz LVDS Reciever with Input Termination
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SGIO_IO_T065GP-LVDS33_TX_CUP - 3.3 V, 675 Mhz LVDS Transmitter
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SGIO_IO_T065GP-LVTTL33_ATB_CUP - 2.5 / 3.3 V Bidirectional LVTTL I/O combined with Analog Test Bus (ATB)
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SGIO_IO_T065GP-LVTTL33_CUP - 2.5 / 3.3V Bidirectional LVTTL I/O with Programmable Drive, Schmitt Trigger & Pull-Up/Down
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SGIO_IO_T065GP-LVTTL33_OD_CUP - 2.5 / 3.3 V Bidirectional LVTTL Input and Open Drain Output
Features

SGIO_IO_T065GP-POWER - I/O & Core Power Pads Along with Power-down Detector
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Silicon based supercap provides a 2X increase in effective capacitance and dynamic power reduction in mixed signal,digital, and switching systems
CC_100IP
Features

SiPro™ PCI Express IP
Features

SMIC11 IO---SMIC 0.13um IO Library
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SMIC13 IO---SMIC 0.13um IO Library
Features

SMIC13-IO-01 - SMIC 0.13um General Process, 1.2V/2.5V Standard I/O Library
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SMIC13-IO-02 - SMIC 0.13um General Process, 1.2V/3.3V Standard I/O Library
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SMIC13LL IO---SMIC 0.13um LL IO Library
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SMIC15 IO
Features

SMIC15-IO - SMIC 0.15um IO Library
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SMIC15_SSTL2IO_01
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SMIC15_SSTL3IO_01
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SMIC15LV-IO - SMIC 0.15um LV IO Library
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SMIC16 IO---SMIC 0.16um IO Library
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SMIC16_VPPIO_01---VeriSilicon SMIC 0.16um 1.8V/3.3V VPPIO_01 IO Library
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SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
SMIC18_MULTIO_02
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SMIC18 General process, Multi-Voltage IO, High ESD perfermance
SMIC18_MULTIO_03
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SMIC18-IO - SMIC 0.18um IO Library
Features

SMIC18_ANALOGIO_05---VeriSilicon SMIC 0.18μm 1.8V/3.3V ANALOGIO_05 IO Library
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SMIC18_ANALOGIO_DUP_05
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SMIC18_CFIO_01
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SMIC18_DUPIO_01 - SMIC18 General process, Device Under Pad, Inline and Stagger standard I/O
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SMIC18_DUPIO_01---SMIC18 General process, Device Under Pad, Inline and Stagger standard I/O
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SMIC18_LVDSIO_01---SMIC 0.18um LVDS Transceiver Pad
Features

SMIC18_MULTIO_02 - SMIC18 General process, Multi-Voltage IO, driver current: 10mA~80mA
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SMIC18_MULTIO_03 - SMIC18 General process, Multi-Voltage IO, High ESD perfermance
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SMIC18_MULTIO_DUP_07---SMIC18 General process, Multi-Voltage IO with high voltage voltence
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SMIC18_OSCIO_01---SMIC 0.18um Crystal Oscillator IO_01
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SMIC18_PCIIO_01---SMIC 0.18um PCI I/O Cells Library
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SMIC18_PCIIO_01---VeriSilicon SMIC 0.18μm PCI I/O Cells Library
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SMIC18_PCIIO_DUP_01---SMIC 0.18um PCI I/O Cells DUP Library
Features

SMIC18_PCIX_02 - SMIC 0.18um PCI-X IO
Features

SMIC18_PCIX_02---SMIC 0.18um PCI-X IO
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SMIC18_SSTL18C2IO_01
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SMIC18_SSTL2IO_01
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SMIC18_SSTL3IO_01
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SMIC18_VPPIO_01---VeriSilicon SMIC 0.18µm 1.8V/3.3V VPPIO_01 IO Library
Features

SMIC18_VPPIO_DUP_01
Features

SMIC25-IO - SMIC 0.25um IO Library
Features

SMIC25-IO---SMIC 0.25um IO Library
Features

SMIC25_SSTL2IO_01---SMIC 0.25um 2.5V/3.3V SSTL2 I/O Cell Library
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SMIC25_SSTL3IO_01---SMIC 0.25um 2.5V/3.3V SSTL3 I/O Cell Library
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SSTL2 Class I & Class II
Features

SSTL_18 (Stub Series Terminated Logic for 1.8v) is an electrical interface commonly used with DDR2.
S13_SSTL18IO_01
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T13V25_DUPIO_01
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T13V33_DUPIO_01
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TSMC 40LP
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TVS UART UVM VIP
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UMC18_CFIO_01---VeriSilicon UMC 0.18μm CF I/O
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UMC18_MULTIO_01---VeriSilicon UMC 0.18um 1.8V/3.3V Multiple I/O
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W65C22S
Features

XAUI PHY IP Core
Features

XpressLite PCI Express x1 Controller for LatticeECP2M FPGAs
Features

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Displaying 201-286/286