ANAHEIM, Calif. — (BUSINESS WIRE) — June 14, 2010 — Design Automation Conference 2010 takes place June 13 - 18, 2010 at the Anaheim Convention Center in Anaheim, CA.
Links to important information:
Business Wire is the official newswire for the Design Automation Conference 2010. Breaking news releases, advisories, photos, multimedia, and press kits from Design Automation Conference exhibitors are available at TradeshowNews.com, Business Wire's trade show, conference, and event news resource.
Listed below are Design Automation Conference exhibitor profiles.
| Company: | Agnisys, Inc. | |
| Booth: | 359 | |
| Media Contact: | Anupam Bakshi | |
| Phone: | 978-631-0505 | |
| E-mail: | ab@agnisys.com | |
| Web: | http://agnisys.com | |
| Agnisys creates automation tools for Verification Planning and Register Specification. It also offers services in Verification, Verification Automation, Register Spec management, and bridging the gap between documentation and reality. | ||
| Agnisys’ award winning product IDesignSpec comprehensively manages register maps for complex designs. Engineers describe the register map and all derived views are automatically generated from it, thus reducing costs and improving quality. | ||
| IVerifySpec is an enterprise class product that enables teams to collaborate and verify complex SoCs. Teams create verification plan in a browser and keep it synchronized with the requirements, regression environment and bug tracking system. | ||
| Company: | Altos Design Automation | |
| Booth: | 1367 | |
| Media Contact: | Liz Massingill (831-345-4702) | |
| Phone: | 408-980-8056 | |
| E-mail: | info@altos-da.com | |
| Web: | www.altos-da.com | |
| The Ultrafast IP Characterization Company. | ||
| Altos Design Automation (www.altos-da.com) provides ultra-fast tools for IP characterization (standard cells, I/Os and embedded memories). Utilizing Altos’ unique “inside view” technology advanced timing, noise and low power views (CCS, ECSM) can be created in hours not days. In addition, Altos provides products for comprehensive library validation and the ability to generate statistical timing libraries for both cells and memories, including accounting for global and local process variation. | ||
| Company: | ATEEDA | |
| Booth: | 1016 | |
| Media Contact: | David Hamilton | |
| Phone: | 44 7905 693 184 | |
| E-mail: | David.Hamilton@ateeda.com | |
| Web: | www.ateeda.com | |
| New for DAC 2010 - Pushbutton BIST for 16-bit ADCs. | ||
| Following success in volume production, ATEEDA is launching a new 16-bit variant of LinBIST for ADCs at DAC 2010. LinBIST helps all semiconductor companies (whether IDM or Fabless) take advantage of the cost-savings associated with Built In Self Test for ADCs and DACs. ATEEDA's tools use smart algorithms to deliver BIST with restricted digital gates and minimal analog circuitry. | ||
| ATEEDA. Cutting the cost of analog test. | ||
| Company: | Atrenta Inc. | |
| Booth: | 744 | |
| Media Contact: | Charu Puri / Liz Massingill | |
| Phone: | 408-453-3333 | |
| E-mail: | cpuri@atrenta.com / liz@leepr.com | |
| Web: | www.atrenta.com | |
| Atrenta is the leading provider of Early Design Closure® solutions that radically improve the efficiency of integrated circuit design. Using Atrenta’s comprehensive tool suite for architectural chip assembly and RTL analysis, customers can create robust and correct designs rapidly, preventing expensive and tedious iterations during the implementation phase. With over 150 customers worldwide, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start! | ||
| Company: | Cybereda | |
| Booth: | 164 | |
| Media Contact: | Graham Bell | |
| Phone: | 408-772-2128 | |
| E-mail: | gbell786@yahoo.com | |
| Web: | http://www.cybereda.com | |
| Come discover PCSIM — the new generation transistor-level simulator for analog designers, and ADDS — a breakthrough analog circuit debugger. With its unique CyberParallel™ technology, PCSIM delivers 10X better runtimes versus popular commercial SPICE simulators with no compromise in precision of results. ADDS attacks the productivity gap in analog circuit debug and delivers a 10X reduction in time spent bug killing. With over 40-years of experience in numerical analysis, circuit simulation, and circuit design, the Cybereda team understands analog design. Cybereda has offices in Silicon Valley, California and Suzhou, China. | ||
| Company: | Duolog Technologies | |
| Booth: | 568 | |
| Media Contact: | Fearghal Hannaway | |
| Phone: | 353 87 915 6418 | |
| E-mail: | fearghal.hannaway@duolog.com | |
| Web: | http://www.duolog.com | |
| Duolog, The Collaborative Design Automation™ Company, is a pioneering developer of groundbreaking EDA tools that enable the flawless and rapid integration of today's increasingly complex SoC, ASIC and FPGA designs. Duolog's Socrates Chip Integration Platform enables IC designs that are Perfect By Construction™. The world's leading IP and IC/SoC development companies rely on Duolog tools to automate their chip integration processes - eliminating bugs, shrinking design cycles and drastically reducing the risk of costly delays and respins. | ||
| Company: | EDACafe.com | |
| Booth: | 1015 | |
| Media Contact: | Graham Bell | |
| Phone: | 408-850-9246 | |
| E-mail: | Graham@EDACafe.com | |
| Web: | http://www.edacafe.com | |
| Thousands of IC, and system designers visit EDACafé.com to learn about the latest company news and research the latest design tools and services. As the #1 EDA portal it attracts more than 75,000 unique visitors each month and leverages TechJobsCafe.com to bring you targeted job opportunities. EDACafé reaches out to more than 30,000+ EDA professionals with its daily CaféNews. EDACafe will be doing video interviews of industry executives at its DAC booth. Please visit to hear all the conference buzz. | ||
| Company: | Grid Simulation Technology | |
| Booth: | 1262 | |
| Media Contact: | Graham Bell | |
| Phone: | 408-772-2128 | |
| E-mail: | gbell786@yahoo.com | |
| Web: | http://gridsimtech.com | |
| GRID Simulation Technology, Inc. is a Silicon Valley-based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology. The company's flagship products, NanoRAIL™ and SimCHECK™, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results. The company is a privately held California Corporation headquartered at the southern extent of Silicon Valley in Morgan Hill, CA and with offices located in: Los Angeles, CA; East Fishkill, NY; and Tokyo, Japan. | ||
| Company: | Methodics LLC | |
| Booth: | 1622 | |
| Media Contact: | Joe Fowler | |
| Phone: | 408-410-2451 | |
| E-mail: | joe@jcfcomm.com | |
| Web: | www.methodics-da.com | |
| Methodics develops next generation Data Management tools for IC Designers. Our VersIC tool seamlessly integrates the industry leading Configuration Management tools, Subversion and Perforce, and enables standard software methodologies to be used as part of an IC design methodology. Our enterprise IP delivery tool and project management tool, ProjectIC, allows organizations to deliver IP, track usage and catalog IP for reuse and generally expedite the delivery of project IP across remote sites. | ||
| Company: | Runtime Design Automation | |
| Booth: | 1349 | |
| Media Contact: | Frank Bailey / Ed Lee | |
| Phone: | 408-492-0944 | |
| E-mail: | bailey@rtda.com / ed@leepr.com | |
| Web: | http://www.rtda.com | |
|
Runtime Design Automation reduces design cycle time & minimizes license & hardware cost while allowing you to finish faster & improve the quality of your design. |
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| Products include: | ||
| •LicenseMonitor tracks license usage, identifying hot spots and under-utilized resources. | ||
| •Workload Analyzer lets you simulate future workloads, so you can plan your EDA and hardware budgets effectively. | ||
| •NetworkComputer manages multiple compute farms, with a high-speed scheduler and the ability to match jobs to machines based on resource requirements. | ||
| •FlowTracer allows you to describe your flows simply, and to deploy them reliably. By tracking dependencies, it avoids redundant tool execution which cuts time and cost. | ||
| Company: | Sagnantec | |
| Booth: | 542 | |
| Media Contact: | Coby Zelnik / Ed Lee | |
| Phone: | 408-727-6290 | |
| E-mail: | coby@sagantec.com / ed@leepr.com | |
| Web: | www.sagantec.com | |
| Migrating Custom IP to Any Foundry/Process. | ||
| Migrate analog and mixed-signal IP, library, memory, CPU and complete hierarchical designs to any foundry 65, 45 and 32 nm process technologies using Sagantec process migration automation tools. With an order of magnitude productivity combined with handcrafted quality and control, you can accelerate time to tape-out as well as improve reliability, EM and yield. | ||
| Company: | Tanner EDA | |
| Booth: | 1342 | |
| Media Contact: | Linda D Marchant | |
| Phone: | 919-451-0776 | |
| E-mail: | linda.marchant@cayennecom.com | |
| Web: | www.tannerEDA.com | |
| Tanner EDA provides a powerful full-flow suite for design, layout and verification of analog ICs and MEMS in use by over 5,000 customers. Tools delivers just the right mixture of features, functionality and usability, allowing customers to create innovative applications in areas like power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership. Visit Booth #1342 to see the latest product release and a new breakthrough analog acceleration tool for device & structure generation. | ||
| Company: | True Circuits, Inc. | |
| Booth: | 1356 | |
| Media Contact: | Stephen G. Maneatis | |
| Phone: | (650) 949-3456 | |
| E-mail: | sgm@truecircuits.com | |
| Web: | www.truecircuits.com | |
| True Circuits develops and markets a broad range of timing IP for the semiconductor, systems and electronics industries. Our robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading fabs, IDMs and design service providers allow us to quickly and reliably produce new and innovative timing IP in a variety of advanced process technologies. TCI offers a complete family of high quality, low-jitter and standardized PLLs and DLLs in a range of frequencies, multiplication factors, sizes and functions in TSMC, GlobalFoundries, UMC and Common Platform processes from 180nm to 28nm. | ||
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