EVE’s New ZeBu-Server Offers Fast Compile Time
[ Back ]   [ More News ]   [ Home ]
EVE’s New ZeBu-Server Offers Fast Compile Time

ZeBu-Serve Software Compiles 200-Million Gate Design in Less Than 10 Hours, One-Billion Gate Design in Less Than 12 Hours

SAN JOSE, Calif. — (BUSINESS WIRE) — September 15, 2009EVE, the leader in hardware/software co-verification, today said that its new emulation system ZeBu-Server offers fast compile times that range from five- to 30-million gates per hour on PC farms, depending on the design’s complexity.

In a recent benchmark, ZeBu-Server software compiled a 200-million gate design in less than 10 hours, and a one-billion gate design in less than 12 hours.

With its fully parallel synthesis, partitioning and place and route features, ZeBu-Server can accelerate first-time compilation, while an incremental compilation capability speeds design changes. The compiler includes a multicore acceleration capability to break the linearity of the compile time on large designs. It can increase compilation speed to a maximum of 100-million gates per hour on designs with hundreds of million gates.

ZeBu-Server offers automated, fast and incremental compilation from SystemVerilog, Verilog and VHDL register transfer level (RTL) code. As an interactive hardware/software debugging tool, it includes complete RTL signal waveform dumping and support for SystemVerilog Assertions.

Priced from $150,000, it is suitable for all system-on-chip (SoC) verification needs across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation.

About EVE

EVE is the worldwide leader in hardware/software co-verification solutions, including hardware description language (HDL) acceleration and extremely fast emulation, with installations at nine of the top 10 semiconductor companies. EVE products significantly shorten the overall verification cycle of complex integrated circuits and electronic systems designs. Its products also work in conjunction with popular Verilog, SystemVerilog, and VHDL-based software simulators from Synopsys, Cadence Design Systems and Mentor Graphics. Its United States headquarters are in San Jose, Calif. Telephone: (408) 457-3200. Facsimile: (408) 457-3299. Corporate headquarters are in Palaiseau, France. Telephone: (33) 1 64.53.27.30. Fax: (33) 1 64.53.27.40. Email: Email Contact. Website: www.eve-team.com.

EVE acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:

EVE USA
Lauro Rizzatti, 408-457-3201
General Manager
Email Contact
or
Public Relations for EVE
Nanette Collins, 617-437-1822
Email Contact