Because of Virage Logic’s proven track record of success at the 40nm process technology that includes multiple customers in production, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare™ Memory compilers and advanced embedded memory test and repair capabilities of the STAR™ Memory System for their first 32/28nm chip.
“Every new process node brings new manufacturing challenges that can impact overall design schedules and time to yield. At the advanced process nodes such as 32/28nm, the industry’s leaders will carefully select partners that enable them to proceed with confidence,” said Brani Buric, executive vice president of marketing and sales at Virage Logic. “With more than ten 40nm customers, Virage Logic has once again proven that it has the technology leadership and know-how to provide its customers with early access to IP that meets their SoC design performance, cost and yield/ramp to volume goals.”
About Virage Logic's Memory and Logic Products
The SiWare product line, first introduced in October 2007 for the 65nm process and now in use by more than 10 customers on the 40nm process, has been proven to address the increasingly complex design requirements that are placed on physical IP at advanced processes. The power-optimized memories for advanced processes minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship embedded memory test and repair system that may be used with Virage Logic memories as well as with other commercially available or internally developed memories. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.
The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications at 40nm with multiple threshold process variants. SiWare Logic libraries offer three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Logic Ultra-Low-Power extension libraries also provide designers with the most advanced power management capabilities.
Virage Logic at DAC
Virage Logic will be a featured partner in TSMC’s Open Innovation Platform™ booth (#822) at the Design Automation Conference (DAC) being held July 27-30, 2009, at the Moscone Convention Center in San Francisco, California. The company will be showcasing its broad portfolio of highly differentiated IP and will have its IP experts available to answer questions.
For further information about Virage Logic's highly differentiated IP product portfolio please visit www.viragelogic.com or email Virage Logic at Email Contact.
About Virage Logic
Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company’s highly differentiated product portfolio includes embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions. As the industry’s trusted semiconductor IP partner, foundries, IDMs and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume. For further information, visit http://www.viragelogic.com.
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