The Session T3 tutorial titled, “Power Reduction Techniques and Flows at RTL and System Level,” will describe several approaches to power reduction at the register transfer level (RTL) and system level. Attendees will gain an understanding of the various electronic design automation (EDA) tools and flows that can utilize standardized power intent formats for functional verification, RTL power optimization, logic synthesis and physical design. Qi Wang, senior architect in the Front End Design Group of Cadence Design Systems, co-authored the tutorial paper and will share presentation duties with Dr. Mathur.
For more details on Calypto, go to: www.calypto.com.
To find out more about the VLSI Conference, visit: http://vlsiconference.com/vlsi2009/.
About Calypto
Founded in 2002, Calypto Design Systems, Inc. empowers designers to create high-quality, low-power electronic systems by providing best-in-class power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information can be found at: www.calypto.com.
Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.
Contact:
Public Relations for Calypto Design Systems
Nanette Collins,
617-437-1822
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