Mentor’s inFact tool achieves superior functional coverage by algorithmically traversing multiple rule-graphs and synthesizing testbench sequences on-the-fly during simulation. The rule-graphs are derived from interface descriptions, bus protocols, functional specifications, or test plans. While rule-graphs are much smaller than conventional testbenches, they allow large quantities of sequences to be generated. However, unlike traditional constrained random test techniques, rule-graphs enable non-redundant sequence generation, eliminating waste of simulation time and resources.
Recent enhancements to the inFact tool enable large simulations to be distributed across multiple CPUs, allowing non-redundant sequence generation to take full advantage of existing simulation server farms. This massive gain in efficiency is attributable to the inherent architecture of rule-graphs and new advanced traversal algorithms tuned for production applications.
A spatial distribution algorithm prevents repetition of sequences on any given simulation CPU, and a modulo-N algorithm prevents repetition of sequences across the entire simulation farm. The same simulation of millions of sequences that requires one thousand hours of run-time on a single CPU can be completed in just minutes longer than ten hours on a simulation farm of one hundred similar simulation CPUs.
However, the power of rule-graphs for production simulation is only partially realized when it assumes that all simulation CPUs are equivalent, all are available for distribution 100% of the time, and that all testbench sequences require the same amount of simulation time. In a more realistic situation, not all CPUs in a server farm may be equally configured, not all may be available for the duration of a simulation run, and every testbench sequence may take a different amount of time to simulate.
To address these complexities, the inFact Simulation Distribution Manager breaks up the universe of sequences into smaller virtual slices and assigns a new slice to each simulation CPU when it has completed previous slice or when it becomes available altogether. This provides an automatic load-balancing effect, preventing the situation where one simulation CPU finishes quickly and waits idly while others finish. It also uses every available simulation resource efficiently, including CPUs that become available after finishing other jobs.
“The architecture of inFact enables staggering productivity enhancements in system verification and can leverage large simulation farms with great efficiency,” said Serge Leef, general manager of Mentor Graphics’ System-Level Engineering Division. “With enhancements like these, Mentor continues to demonstrate its leadership in testbench technology.”
Pricing and Availability
The latest version of inFact is available immediately at a starting price of $75K.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $850 million and employs approximately 4,200 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics is a registered trademark and inFact is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
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