SAN JOSE, Calif.—(BUSINESS WIRE)—June 4, 2008— Apache Design Solutions, the technology leader in power, noise, and reliability (PNR) signoff for chip, IC package, and system designs, today announced that Hynix Semiconductor, Inc. has adopted Apache’s RedHawk dynamic power integrity solution for their DRAM designs. Hynix will use RedHawk’s full-chip transistor-level dynamic power analysis capability to analyze and validate their full-custom DRAM designs to identify dynamic “hot-spots” caused by power/ground weaknesses, as well as perform accurate electromigration analysis to eliminate false violations that can result in long design closure. RedHawk’s transistor-level feature provides both performance and capacity required to verify the entire DRAM design, while maintaining fast Spice-level accuracy. By using RedHawk, designers of full-custom designs such as DRAM and Flash memory can directly analyze their GDS database and use layout-based GUI for debugging.

“Power and noise issues are one of the top concerns for our memory designs but using traditional tools such as Spice or fast Spice is not feasible due to their performance limitations,” said Dr. Young Doo Choi, senior member of technical staff from Hynix. “Apache’s RedHawk was able to perform dynamic power analysis within a day on an entire DRAM and produced results that closely correlated to our Spice simulation. With the performance and accuracy of RedHawk, we can now verify all of our DRAM designs, further increasing our confidence in the quality of design.”

“As memory designs move towards 50nm class and below, more and more companies are requiring power as one of the signoff criteria,” said Dian Yang, senior vice president of product management and general manager of Asia at Apache. “The transistor-level feature of RedHawk leverages its technology for SoC power integrity to deliver the capacity, performance, and accuracy needed to perform full-custom power analysis.”

About RedHawk

RedHawk is a full-chip Vectorless Dynamic™ physical power integrity solution for SoC power signoff of nanometer designs. Correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk delivers transistor-level accuracy with cell-based capacity, performance, and ease-of-use.

With RedHawk, designers can identify dynamic “hot spots,” examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. RedHawk enables designers to reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, MTCMOS (power-gating), multiple voltage domains, and multiple threshold transistors.

About Apache Design Solutions

Apache delivers the leading power signoff solution adopted by 80% of the top IDM, fabless semiconductor, and foundries and a complete platform for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache’s innovative platform considers multiple noise sources that impact the design--such as power, signal, package / system IO, substrate, and temperature—and enables designers to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon and/or system. Apache’s vendor-neutral solution supports any industry-standard physical design flow and is certified by TSMC and Common Platform Reference Flows. Apache is a global company with R&D centers and direct sales / support offices worldwide. For more information, visit www.apache-da.com.

Apache Design Solutions, NSPICE, RedHawk, PakSI-E, PsiWinder, Sahara, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.

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