MEDIA ADVISORY: Meet With Leading IP Suppliers at IP Talks! at DAC
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MEDIA ADVISORY: Meet With Leading IP Suppliers at IP Talks! at DAC

ANAHEIM, CA -- (MARKET WIRE) -- Jun 03, 2008 --


WHAT

IP Talks! returns to DAC this year, providing an opportunity for conference attendees to meet with leading IP suppliers to learn how the latest in semiconductor IP can help them accelerate their design success. Sponsored by the ChipEstimate.com chip planning portal, IP Talks! features ChipEstimate.com partners delivering technical presentations on the latest in semiconductor IP.

DAC attendees also are invited to a free breakfast and panel discussion the morning of June 11. EDN Magazine Executive Editor Ron Wilson and four panelists -- from Sidense, ChipEstimate.com, Synopsys and Tensilica -- will tackle the question, "Can IP integration be an SoC methodology, or is it always ad hoc?"

WHEN

IP Talks! are June 9-12. See the schedule at www.chipestimate.com/dac2008/. The breakfast panel is at 8 a.m. June 11.

WHERE

IP Talks! will take place at Booth 2358, Anaheim Convention Center, Anaheim, Calif. The breakfast will be in the Carmel Room, on the fourth floor of the Hilton Anaheim.

About ChipEstimate.com

The ChipEstimate.com chip planning portal is an ecosystem comprised of over 185 of the world's largest IP suppliers and foundries. These companies all share in the common vision of helping the worldwide electronics design community achieve greater profitability and success. To date, a diverse global audience of over 16,000 users has joined the ChipEstimate.com community and has collectively performed over 60,000 chip estimations. ChipEstimate.com is a property of Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation.

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.

Email Contact
408-944-7226