SAN JOSE, Calif.—(BUSINESS WIRE)—May 30, 2008— Tela Innovations, an early-stage technology company focused on addressing the challenges of scaling semiconductor manufacturing to 45nm and beyond, will showcase its innovative chip design technology at two upcoming industry events. The company will make presentations and demonstrate its technology at the Applied Materials Technical Symposium at IITC (International Interconnect Technology Conference) on June 2, 2008 in San Francisco, and the following week at the 2008 Design Automation Conference June 8-12 in Anaheim, California.

Tela will use both venues to discuss and demonstrate its solution for using on-grid, straight-line, one-dimensional layout structures to provide a more efficient and reliable way to design and manufacture next generation chips. The solution uses pre-defined physical topologies, applicable for use in logic, embedded memory, analog and I/O functions. The resulting benefits for designers, equipment suppliers and manufacturers include improvements in variability, performance, leakage and area without significant impact on existing design methodologies, equipment sets or process technologies.

At IITC, Tela will participate in a technical symposium put on by Applied Materials ( http://www.appliedmaterials.com/2008_IITC/). The event begins at 5PM on June 2 at the San Francisco Airport Hyatt Regency. Tela President and CEO Scott Becker will be featured on a panel discussion titled “New Dimensions to Moore’s Law,” which will look at how circuit design optimizes performance and yield. Becker will touch upon the limitations of current design and lithography approaches that stand in the way of continued scaling of semiconductor processes.

At the 45^th annual DAC ( www.dac.com), Tela will have an exhibit in Booth # 473 at the Anaheim Convention Center, where it will demonstrate its solution that consists of regular-patterned, pre-defined topologies. When synthesized and routed as part of the overall design, the solution enables a lithography-optimized layout. Tela will also have a featured presentation in the Exhibitor Forum at DAC on Wednesday, June 11 at 10:30AM. That presentation, titled “45nm Leakage Reduction Using Gridded, One-dimensional Layout,” will be held in Booth # 2849 in Exhibit Hall D and present 45nm test chip results.

In early test cases, Tela’s solution has proven to reduce area, improve performance and limit leakage in designs targeting advanced processes. One customer test case resulted in a 15% area reduction and a 2.5x reduction in leakage using a 45nm process. In addition, the cells and resulting blocks created using the Tela solution have been successfully implemented using existing production design flows and tools.

To sign up for a private demonstration of Tela’s solution at DAC, go to http://www.tela-inc.com/dac.php.

About Tela

Tela Innovations is a privately-held company based in Campbell, California that is addressing a fundamental challenge in the scaling of semiconductor technology to keep pace with Moore’s Law. The Tela solution introduces a new approach that uses gridded, straight line, one dimensional layout structures that produce logic blocks with a lower k₁ lithography limit. By restricting the number and type of interactions between shapes, it helps overcome the limitations of current lithography techniques. The solution works within standard EDA and physical design methodologies.

Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology. It has received funding from Sand Hill Finance Company and Teton Capital Company, Intel Capital, AsiaTech Investment and Western Technology Investment. More information can be found at www.tela-inc.com.

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Contact:

Tela Innovations, Campbell, Calif.
Neal Carney, 408-558-6322
Email Contact
or
Wired Island
Mike Sottak, 408-876-4418
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