At 200 MHz, the SH7652 32-bit superscalar microcontroller offers 480 MIPS (million instructions per second) of CPU performance and abundant processing power to handle both content protection and encryption/decryption functions for IP Broadcasting and DTCP-IP. The SH7652 features an IEEE-802.3 standard(a)(4) compliant media access controller (MAC)(a)(5) interface that supports connection speeds of up to 10/100Mbps and allows simultaneous transmission of two-channel HD digital content. The two-channel video stream port allows high-speed transfer of MPEG-2(a)(6) TS (Transport Stream) and MPEG-2 PS (Program Stream) format data. The video stream port allows an easy interface to an MPEG-2 encoder/decoder chip, facilitating high speed network transmission of MPEG-2 TS format video data. The on-chip hardware encryption block enables high-speed encryption of content data, allowing HD digital content to be transmitted over the network with ease.
An impressive array of on-chip peripherals and interfaces such as a High-Speed compliant USB 2.0 host/function and SD memory card host interface allow seamless connections to a memory card and wireless LAN modules. Audio support is provided through the Serial Sound Interface (SSI) for playback of MP3, WMA (Windows Media(R) Audio), and other audio formats.
The SH7652 can be easily integrated into a multiprocessor system with its on-chip host interface. The SH7652 communicates with the host CPU using a 16-bit SRAM like memory interface that provides a simple handshake for connection with the host system. CPU tasks associated with copyright protection and network processing can thus be independently handled by the SH7652 microcontroller without imposing a burden on the host CPU, simplifying the overall development process.
A comprehensive range of peripheral functions is also incorporated into the sophisticated SH7652 device, including a hardware accelerator that performs TCP/IP checksum computations automatically without software intervention. The SH7652 handles error-correction and encryption/decryption functions for content protection in firmware, which is provided with the device. The device also supports WM DRM10(a)3 copyright protection.
Support tools are available to facilitate the system design process. Renesas offers an integrated development environment with software tools, evaluation boards, and the low-cost Renesas E10A on-chip debug emulator.
Renesas Technology will continue to extend its lineup of products that have on-chip Ethernet controllers. Future devices under consideration include chips that will offer faster CPU performance, wireless LAN support, and enhanced peripheral functions.
Product Name Maximum Operating Package Sample Price /
Frequency Availability
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SH7652:(R5S76520B200BG) 200MHz 240-pin CSP $17 / January
(13mm x 13mm) 2007
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Reader contact
Readers can find additional product and contact information on the Renesas Technology Web site at www.renesas.com.
About Renesas Technology Corp.
Renesas Technology Corp. is one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets and the world's No.1 supplier of microcontrollers. It is also a leading provider of LCD Driver ICs, Smart Card microcontrollers, RF-ICs, High Power Amplifiers, Mixed Signal ICs, System-on-Chip (SoC), System-in-Package (SiP) and more. Established in 2003 as a joint venture between Hitachi, Ltd. (TOKYO:6501) (NYSE: HIT) and Mitsubishi Electric Corporation (TOKYO:6503), Renesas Technology achieved consolidated revenue of 906 billion JPY in FY2005 (end of March 2006). Renesas Technology is based in Tokyo, Japan and has a global network of manufacturing, design and sales operations in around 20 countries with about 26,200 employees worldwide. For further information, please visit http://www.renesas.com
Note to Editors: A specification summary is included in this release, and a photo and block diagram of the SH7652 microcontroller are available.
Notes: 1. IP broadcasting refers to the distribution of TV broadcasts
via the Internet.
2. DTCP-IP (Digital Transmission Contents Protection over
Internet Protocol) is a standard for IP network content
protection, standardized by the DTLA (Digital Transmission
Licensing Administrator). The SH7652's DTCP-IP support
functions were developed by Renesas Technology using
technology developed by Hitachi, Ltd.
3. WM DRM10 (Windows Multi Media DRM10) is a digital copyright
technology developed by Microsoft Corporation. Microsoft,
Windows, and Windows Media are registered trademarks or
trademarks of Microsoft Corporation in the United States
and other countries.
4. IEEE-802.3: IEEE-802 is the title of an IEEE (Institute of
Electrical and Electronics Engineers) committee for
promoting LAN standardization. IEEE-802.3 is a CSMA/CD
10/100Mbps Ethernet LAN specification standard. In CSMA/CD
(Carrier Sense Multiple Access with Collision Detection),
the presence of a carrier is detected before transmission,
and if a collision is detected during transmission, the
system waits for a predetermined time before restarting
transmission.
5. MAC (Media Access Control): A lower sub-layer within the
data-link layer, stipulating the frame
transmission/reception method, frame format, data error
detection, etc.
6. MPEG-2 (Moving Picture Experts Group phase 2) is a video
data-compression method comprising part of the MPEG
standard.
(a)SuperH is a trademark of Renesas Technology Corp. Other
product names, company names, or brands mentioned are the
property of their respective owners.
Specifications: Renesas Technology SH7652 Microcontroller with IP
Broadcasting and DTCP-IP Copyright Protection Support
Item SH7652 Specifications
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Part Number R5S76520B200BG
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Power supply voltage 1.2V (internal) / 3.3V (external)
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Maximum operating frequency 200MHz
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Maximum processing performance 480 MIPS (at 200MHz operation)
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CPU core SH2A-FPU (built-in double-precision
floating-point unit)
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On-chip RAM 32Kbytes
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Cache memory 8Kbyte instruction cache memory, 8Kbyte
operand cache memory (4-way set-
associative type)
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External bus interfaces SH local bus controller
-- SRAM, SDRAM, ROM directly
connectable, PCMCIA interface provided
-- Data bus width: External 8/16/32
bits
----------------------------------------
Host interface function
-- 16-bit bus width SRAM type interface
-- Incorporates 2Kbyte x 2-bank buffer
RAM
----------------------------------------
On-chip peripheral functions Copyright-protection support functions
-- Encryption algorithms
(AES/DES/3DES/MUGI): 1-block
processing also possible
-- Hash algorithms (SHA-1/SHA-224/SH-
256)
-- Message authentication code
generation (HMAC-SHA-1/HMAC-SHA-
224/HMAC-SH-256)
-- Dedicated DMA controller with built-
in descriptor function x 2 channels
-- TTS (Time-stamped Transport Stream)
packet analysis
-- ProMPEG-type forward-error-
correction function
----------------------------------------
Video stream interface x 2 channels
-- Serial/parallel switching possible
-- Both MPEG TS and MPEG PS supported
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Ethernet controller x 1 channel
TCP/IP checksum-accelerator function
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Dedicated Ethernet controller DMAC x 2
channels (1 channel each for
transmission and reception)
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General-purpose DMA controller x 8
channels
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Serial sound interface (SSI) x 2
channels
-- Bidirectional serial transfer
-- Various serial audio formats
supported
----------------------------------------
USB 2.0 Host/Function module x 1
channel
-- High Speed/Full Speed/Low Speed
supported
-- Hub function supported
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SD host interface (SDHI) x 1 channel
-- SD memory/IO card interface (1-
bit/4-bit SD bus)
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I(2)C bus interface x 1 channel
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Serial communication interface with
FIFO (SCIF) x 3 channels (asynchronous
and synchronous serial communication
capability)
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16-bit compare-match timer (CMT) x 2
channels
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On-chip debugging functions
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Interrupt controller (INTC)
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Watchdog timer (WDT)
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Clock pulse generator (CPG): Built-in
multiplication PLL
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Power-down modes Sleep mode
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Software standby mode
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Module standby mode
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Package 240-pin CSP (13mm x 13mm)
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Contact:
Renesas Technology America, Inc.
Akiko Ishiyama, 408-382-7407
Email Contact