RioMagic is the first commercially available electronic design automation (EDA) software to take into consideration package escape, routability and parasitics and enable simultaneous tradeoffs between chip and package design. Employing an interconnect synthesis approach, RioMagic analyzes a wide range of variables to converge on a final I/O plan. With its embedded chip/package extraction, estimation and simulation capabilities for signal and power integrity, the impact on electrical performance is understood and addressed before final implementation.
"Producing optimal, low-cost silicon is an imperative that has spawned the trend to concurrently design for chip, package and system," says Kaushik Sheth, Rio Design Automation's chief executive officer (CEO).
"What previously took three months, we were able to accomplish in two weeks using RioMagic and reduced the area of our chip by 20 percent," adds Robert Knoth, senior engineer at Tektronix Inc. "This is a remarkable accomplishment."
Introducing RioMagic
"RioMagic has been in use selectively over the past year for a variety flip chip designs and it positively impacted cost, die size and performance of the finished product," reports Egino Sarto, Rio Design Automation's chief technology officer.
Concurs Jerry Lee, senior vice president of engineering and interim CEO of Velogix Inc.: "RioMagic is the first package-aware chip design software solution and a must-have tool for a startup such as Velogix. Since we began using it, we were able to reduce our package design costs. Our design team is pleased with RioMagic and Rio Design Automation's support."
RioMagic's rich feature set lets chip designers develop optimized I/O strategies for the chip and package to improve performance and reduce costs. This is accomplished using a chip/package co-design flow that begins during initial floorplanning before elements within the chip are fixed.
As the design progresses, RioMagic can be used when there are changes in the chip or package design to validate the initial strategy or to re-optimize the I/O plan with the new and updated set of design criteria.
To enable chip/package I/O planning and optimization, relevant data for the chip and package needs to be represented within a single data model. This unified data model facilitates the optimization process by bringing all design elements into the synthesis flow, which means that the entire chip and package can be represented simultaneously. It is integrated using the industry-standard OpenAccess database.
The RioMagic database serves as the repository of the "golden" chip/package interconnect matrix because it is where both chip and package connectivity can be managed in its entirety.
In addition to physical implementation, RioMagic offers extraction and analysis capabilities to approximate signal performance from driver to package ball. On-chip parasitics are extracted using pre-generated look-up tables while resistance, inductance, capacitance (RLC) models are used to calculate RLC package parasitics early in the process for timing and noise analysis.
Through its graphical user interface, RioMagic generates a simulation deck that includes primary drivers, drivers for coupled nets, a coupled net parasitic network and a printed circuit board (PCB) loading termination for each net. The network is analyzed and it calculates the response for the primary net switching and coupling effects from adjacent nets.
Chip data setup is similar to other chip design software -- DEF for chip netlist, intellectual property (IP) libraries for I/O, standard cell and hard macros in LEF and I/O driver models in IBIS.
For package import, data is setup via direct extraction from Cadence's Allegro Package Designer (APD), along with associated techfile rules. Exporting back to APD includes bump/ball assignments, escape routing, voltage domain plane cuts and constraints. For netlist information, RioMagic also supports the import and export from existing customer spreadsheets.
For final verification of the final chip/package design where accurate results are required for final signoff, RioMagic generates SPD files that can be directly read into the Sigrity software.
"RioMagic holds promise for low-cost and highly optimized silicon parts," concludes Ed Linke, director of Assembly and Packaging at TranSwitch. "We've been impressed with its ability to make last-minute changes."
Pricing and Availability
RioMagic runs on the Linux operating system and is priced at $199,000 per year for a three-year, time-based license.
For more details, contact Joel McGrath in Rio Design Automation's technical marketing group. He can be reached at (408) 844-8038, Ext. 15, or via email at jmcgrath@rio-da.com.
About Rio Design Automation
Rio Design Automation is an electronic design automation (EDA) company bridging the gap between the design of high-performance integrated circuits (ICs) and packages, and a chip's integration with the rest of the electronic system. Its revolutionary approach offers chip designers package-aware software to that enables I/O optimization tradeoffs to take place in the context of the package and the printed circuit board (PCB). Founded in 2003, its investors include Cadence Design Systems Inc. (NYSE: CDN), Magma Design Automation Inc. (Nasdaq: LAVA) and private angel investors. Corporate headquarters is located at: 2901 Tasman Drive, Suite 112, Santa Clara, Calif. 95054. Telephone: (408) 844-8038. Facsimile: (408) 844-8945. Email: info@rio-da.com. Website: http://www.rio-da.com.
Package-Aware Chip Design is a trademark of Rio Design Automation. Rio Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Contact:
for Rio Design Automation Inc. Public Relations: Nanette Collins, 617-437-1822 Email Contact