Zenasis Technologies – Hybrid Optimization
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Zenasis Technologies – Hybrid Optimization

Introduction

Zenasis Technologies is a five year old firm that brings transistor-level custom design optimization technology into an automated cell-based flow. Their main product is ZenTime which uses "Hybrid Optimization" to eliminate timing problems and improve the performance of cell-based designs. ZenTime eliminates the negative slack in cell-based design by exploring, identifying, designing, and inserting design-specific standard cells on the fly. The product integrates into most existing cell-based flows because the new cells use the same architecture as the user's basic standard cell library.

I had an opportunity to discuss the company with Dennis Harmon who came on board as President and CEO in July of 2005.

Would you give us a brief overview of your background?
My background is basically 20 plus years in design and design automation. It began back in the early eighties at Viewlogic. There were several other companies since then. Viewlogic was one of the larger ones who went public and subsequently was acquired by Synopsys. In the early 90s I and several others from Viewlogic founded a company called Synchronicity that was focused on deign collaboration tools for the semiconductor industry. That firm was acquired by MatrixOne in 2002. Now I am with Zenasis.

Would you give us a more expanded view of what Synchronicity was up to?
Synchronicity was basically building a product to help design engineers communicate and share information in real time over the Internet. What we built from a product perspective was the ability for companies with large geographically dispersed design teams to effectively work together in an environment where the location of the data was transparent to the users. For example, Intel was one of our largest customers and actually an investor in the company. They used Synchronicity technology and are not created by one group in one building. You'll get cores from different companies. You'll get IP from different companies. You will have design teams dispersed throughout the world working 24 hours a day on chip design. Our technology basically underlayed the EDA environment and provided a means for EDA data to be shared in an effective and efficient manner.

Who was Synchronicity's competition?
Strangely enough there was very little competition from a commercial perspective. The real competition for Synchronicity was internally developed solutions - people putting together scripts, PERL scripts, PDS and various other forms of configuration management tools. Of course the challenge was that it kind of fell apart as soon as you introduce an external partner, for example if you wanted to work with the ARM core team inside your design team. We were probably the only commercial solution and in fact Synchronicity is still the only commercial solution focused on semiconductor design. The uniqueness of that is that we understood all of the EDA data models, i.e. Cadence data base and Synopsys data base. We natively handled very complex data bases. There were some other small companies that did parts of what we did but not in the way we did it.

I am sure you know that the three major high end mechanical CAD vendors (Dassault Systemes with Catia, Unigraphics and PTC with Pro/E) generate significant revenue from PDM (Product Data Management) products and services. There are also MatrixOne and Agile who are focused on PDM and have revenues in excess of $100 million. How come there is no parallel in the EDA industry?
Laugh! That's a great question. It has always boggled our minds. If you think about it in the software industry, which we are in, we take seriously the challenge of managing product lifecycles and managing the process which is very interactive, very team intensive process of developing software. We have very sophisticated tools from companies like Rational Software which is a very large firm and now part of IBM that manages the information to control our software development process. With the mechanical CAD vendors as you mentioned there is the very same thing. Very large companies developing very sophisticated products manage the product lifecycle and the very interactive process of doing mechanical design through computer information tools. Why in the world the electronics industry has not grasped onto that was a confusion point to us. It provided us an opportunity to grown quite a large company. MatrixOne has taken that over and they are extending it from their traditional markets which were outside the semiconductor space into that space. I think that's good news for the semiconductor industry in general. More specifically it is good news for very large design teams that have to deal with this very thorny problem of managing data across their network. Lots of different people touching it. I have talked to many vice presidents and directors of engineering about chip tape outs that have failed not because of any sophisticated timing problem or sophisticated P&R problem but had failed simply because they used the wrong data. It's amazing!

Did Synchronicity seek out potential buyers like MatrixOne or did MatrixOne come a courting?
It was a combination. The way we perceived it, this was a very large problem to solve and for a small company to solve it we thought we would require a fairly large infrastructure. Right form the start of Synchronicity we believed that the way to scale the technology and the company was to find the right partner who had a global infrastructure to support this kind of problem of managing information across a global network. It's the biggest companies with the largest number of engineers that have the problem. In order to effectively support and scale the business we needed to rapidly find someone who could help us do that. So to that extent we sought out companies, in fact companies like Agile who was working on the periphery of the semiconductor space. They do data management of the electronics industry. They do have somewhat of a semiconductor focus but not a real business. And we obviously sought out MatrixOne as well.

How did you get comfortable sharing information with MatrixOne who might have ended up as a more direct competitor?
You know what's interesting is that the semiconductor design space is such a complicated space relative to the other spaces that they were focused on. From their perspective it was a build versus buy decision. If they went down the build road, they would have to gain a significant amount of expertise on semiconductor design, particularly the back end of the design. They couldn't acquire that in a reasonable time organically. As you now, it is very specialized space. We felt very comfortable with our core competency, the ability to have a high barrier to entry if they tried to do it themselves. In addition to that, I was very familiar with the executives over at MatrixOne. They knew what we did and we knew what they did. It worked out quite well.

Enough about the past. Would you give a brief overview of Zenasis, your current company?
Zenasis just turned five years old. It's a company focused on automating the design optimization phase of the semiconductor design flow, specifically standard cell approach to doing design. More specifically, the company is focused on reducing the time it takes design teams to meet the performance spec in effect in less time at lower cost. Before coming on board it was clear to me that they had a vast portfolio of very good technology. They had a great organization of people. I'm kind of quoting Geoffrey Moore's book the Crossing of the Chasm. They did a good job of getting to the chasm in terms of developing the technology and then developing a core group of initial customers and refining the technology. Now the challenge is to take that technology and turn it into whole products, not just the executables but the services, support, documentation and usability that's required to scale and deploy this type of technology across a large organization.

According to the press announcement you joined Zenasis last July. The founder and former CEO, Dr. Roy, moved over to CTO. This is not an uncommon occurrence in the EDA industry. What were your concerns coming into this situation and how has it worked out?
First, it has worked out quite well. I've known Jay Roy since ViewLogic where we worked together for a couple of years. So I knew Jay very well. When you come to a company that has been going for 5 years and has developed such a large portfolio of technology, the real challenge that I saw was how do we take this shotgun approach and turn it into a rifle approach with respect to solving a well known problem in the semiconductor industry. That's what we have been focused on for the last six months; taking this portfolio of technology, finding out the jewels inside that portfolio and really honing them in on very specific problems in the semiconductor design space. The specific problem is reducing the time it takes to do timing closure, quite frankly reducing not only the time but getting the design teams to become more efficient and effective in doing timing closure. The way we do that is by simply automating that process for them. A lot of timing closure today, as you know, is still done by hand because there aren't enough tools out there for engineers and design teams to do timing closure in an effective and efficient manner. That's what we have been focused on.

There are three generic approaches to design, FPGA, standard cell and custom ASIC. Is the standard cell approach just right or does it compromise too much on both ends to be a viable alternative to the others?
I think one of the reasons Zenasis exists and has been focused on this space is that the standard cell approach to ASICS is a compromise. If you have to push the limits of performance on your design and you are using the standard cell approach, then you will be compromising certain aspects of performance in terms of speed, power and area because of the very nature of the process. The initial thrust in terms of our position in the marketplace was to provide some of the benefits of custom design while at the same time using a standard cell approach. Most specifically the technology that we developed did design specific or tactical cell creation. That's where we see ourselves playing a role. Most designs today are done using the standard cell approach. I think most of the design starts over the last several years have been standard cell that included embedded cores from the likes of ARM and MIPS. The challenge of course is because it is a compromise there is a risk in using the standard cell approach. You find design teams struggling to make the design run at spec. That causes delays to market and increase in cost. Any tool that can help the standard cell design team improve the time it takes to get to the performance spec is a valuable tool.

The Zenasis approach is called hybrid optimization
Hybrid optimization is one of the underlying patented technologies that the company has developed. There are other companies out there that attempt to help in that area but take a different approach. The hybrid optimization technology that is part of our optimization platform is one of the root technologies that enables us to solve that problem. More specifically, what hybrid optimization technology does is it analyzes the design at multiple levels of abstraction, namely the gate level, the physical level and the transistor level which is unique and it does this concurrently.

From browsing your website I sense that it tries to figure out areas that would benefit the most from tactical cell creation and then automates that.
It does several things. The key to this whole thing is to remember what design teams are up against. They have these very large, millions of gates, designs that have literally thousands of critical paths. To analyze that through manual methods is a daunting task, in fact next to impossible because of the nature of the approach they take. The first thing Zenasis does is to analyze the design. It does it at all of these three levels using hybrid optimization approach. The key to it is first identifying the path and then identifying the cells in those paths and then the type of cell that might break the bottleneck in that critical path to improve the timing. It does those three things simultaneously and automatically. The other interesting thing about the technology is that you will never get a worse result than you currently have. In other words it always improving the timing of the design or always improving the leakage power of the design. You never take a step back. With manual methods, as you now, because of the nature of the way you have to do it, it is possible that you go through this manual method, fix this particular path and then the timing of that path might improve but the overall timing of that particular block might not improve, In fact you might take a step back. With our approach of looking at all three levels (gate, transistor and physical) and doing it on the fly, we never take a step back which is a great advantage using this type of tool.

Is "tactical cell creation on the fly" pulling existing cells from different libraries with different characteristics or is really creating something new?
There are two things that we do today. One is we can use hybrid optimization to identify the critical path and cells while taking into context the library. Think of it this way, you read in the design and the available library in and the tools tries to find in the first instance the best possible fit for a cell inside the existing libraries or a derivative of that cell inside that library to instantiate to make the timing better. That's level one. Level two is the tool will do the same thing, look at the library and then create an entirely new cell if necessary to improve the timing. So there are basically two modes. One mode where it looks at the design in the context of the available cells in the design library and uses a more effective, a more efficient cell to instantiate to improve the timing And the other mode which tends to get much better performance in the end is to create an entirely new cell from an existing cell.

Are there certain markets or end user applications that would benefit most from your products?
I have been out and met with probably 50 prospects and a dozen or so customers. The design application where we see the best fit for the technology is where the design teams are struggling with high performance design, pushing the limits of the standard cell approach while using an embedded core from ARM or MIPS. The reason is they don't have complete control over the implementation of these cores. They have certain levels of control over the implementation but they bring in these cores from an outside source and they bring in other outside IP and then try to integrate that in. The challenge becomes how you make something perform at spec when you don't control all of the architectural decisions that went into it. From that perspective we see people who are using embedded cores on high speed design. They have the greatest need for this application. ARM is a great example. Someone using an ARM would probably have a use for Zenasis products.

Do you have any relationship or partnership with ARM?
We are in discussion with several core providers including ARM and MIPS. We see that as a great opportunity for both Zenasis and these core providers to improve the timing closure process for our mutual customers. We see that as a very valuable relationship to create and then maintain.

Editor: Zenasis is a member in the ARM® Connected Community

You mentioned that Zenasis had been successful early in landing some key customers. Who are some of your customers?
I can't name a few for the obvious reason that they don't allow you to. I can say that among our customers there are some of the larger if not the largest DSP vendor on earth as well as some of the largest foundry companies. As an example TSMC is an investor. They will ultimately be a fairly large user of the technology. Companies like Renesas Technology and Samsung. At this point the company has been focused on a small set of core customers, particularly in the IDM space because of the need of having to do cell creation. But as we move forward, we have refined the technology to be applicable to a much wider audience of customers and markets including fabless companies.

You brought up an interesting challenge for yourself. You represent to the outside world that your products do wondrous things. The easiest way to prove that would be for existing customers to testify to that. But some of your best customers refuse to acknowledge that they are even using them. How do you overcome this?
It is a paradox. There are many reasons why large customers won't allow small vendors, particularly vendors who provide real value, to announce them to the outside world simply because they look it as a competitive advantage. That's certainly true in this case. By using the technology you can improve time-to-market and reduce cost. You can maximize the performance of your design. Many large companies as many small companies who find a competitive advantage from technology prefer that not everyone knows about that. How do you get over that? You grow your customer base. You get a much larger footprint. Certainly it is much easier to sell to new customers if you can reference successful customers. We do have to play by the rules and that's one of the rules. It's just something you have to overcome. Companies like Samsung are very willing to assist small companies to market their products. In order for them to derive value, we have to be viable. They know we have to grow our customer base. So many companies are open and willing to assist us being a reference for the technology.

Whom do you see as competition out there?
It's interesting. There are a few companies that focus on this space - timing closure, but they certainly don't do it in the same way. Because of our unique and patented hybrid optimization approach and because we look at the design at the gate, transistor and physical level we have a unique advantage in that respect. The real competition is all the other potential solutions to this problem that are done in a different way. A lot of physical synthesis tools attempt to do this type of optimization. They don't do it in the same way obviously. I think our unique approach is the ability to take very large blocks in the design and identify the critical paths, identify the cells in the critical paths that can improve the performance of the critical design and then be able to create a new cell, if that is the right approach to take. There is no one out there that does exactly what we do in the way we do it. I guess that's the way I would summarize the competition. There are other tools that in the same part of the design process that attempt to do the same thing but of course they don't have the same hybrid optimization approach.

Given that you are not a total solution, how well do you fit into the major design flows?
Great question! One of the things I saw when I first came to Zenasis when I was doing my due diligence was the fact that these guys had thought about whether they wanted to use disruptive technology where you have to implement an entirely new flow within an existing EDA environment or whether they wanted to use an augmentation technology where you simply come in and complement the current flows. Clearly the approach that the founders took was to augment existing flows. It is very difficult in large semiconductor companies with established design flows to get them to change flows. When Magma started they had a very difficult time with that. They struggled to overcome that. The approach that Zenasis has taken is to work with all of the existing flows from Cadence, Synopsys and Magma. Essentially that's what we have done. We do it by reading and writing the standard formats in the standard cell design flow for these three EDA vendors.

What is the packaging and pricing of you products?
There are various options to ZenTime ranging form $175K for a one year time based license (TBL) all the way up to $250K for the top of the line TBL for ZenTime if you were to get all of the options - transistor level optimization, leakage power optimization, area optimization.

How many seats would the typical customer have?
This is similar to other implementation tools. The use model is one where a single engineer trying to explore different specs or different constraints on the design would run 5 licenses concurrently to improve the overall run time for getting the final results acceptable. Traditionally we see companies using 5 to 10 licenses concurrently which is not unusual for an implementation tool.

What is Zenasis future product direction?
The focus this moment is primarily timing closure. But of course the counterbalancing parameters are performance, power and area. As we move forward at least in 2006 we will remain focused on shoring up our solutions in the timing closure area. However, to a large extent the infrastructure for doing power optimization and area optimization are built into the platform already. It's now a mater of exposing that in the form of an application as we move forward and evolve the company. Those three performance factors are in the bull's-eye of the type of applications we will be delivering to the marketplace in the next 24 months.

Does the value or need for your product increase as a company moves from 90nm to 65 nm?
In fact many of our existing customers and again one of the largest DSP companies are using the technology to help their 65 nm process. It's actually an interesting side benefit to this technology to be able to analyze libraries and help them generate a set of optimized cell libraries for the types of designs they see and the types of challenges in the new processes that they see because there are many. The value increases significantly as you go from 90 nm to 65 nm and from 65 nm to 45 nm because the challenges become even more critical and more difficult. A lot of our customers today are using the technology to help them migrate to new process nodes. In fact I would say that half of our current customers are using it at 65 nm which is on the leading edge today in terms of design starts. I absolutely believe that the value increases as you go down.

According to your website Zenasis has around 34 employees.
Probably a little bit higher than that. We will certainly be growing that number this year. Primarily we will be focused on building out our application service and support.

Would you give me some numbers on revenue and profitability?
As a private company we don't give out the exact revenue numbers but I can tell you that last year we grew the business 100%. We've also doubled the size of our customer base. It is growing relatively significantly. This year we anticipate another 100% year over year in terms of revenue as well as tripling of our customer base. There are many reasons for that but that's our goal. In terms of profitability, we are a venture backed company. We just completed a round of funding last quarter. We will break even in 2007.

Editor: Zenasis has raised $17 million in venture funding over three rounds.

What is the sales model for Zenasis?
Primarily direct in the large markets in Europe and the US. We have been direct in Asia. We will be adjusting various ways to do sales in Asia on an as needed basis. We have a distributor in Japan and we recently signed up a distributor in Taiwan.

Are your products more suitable for one geography than another?
No. Interestingly enough the issue of timing closure is everywhere you have design teams doing standard cell designs, more specifically doing standard cell designs using embed cores. It's not gated by where it is being designed. We have seen a few products at Philips in Europe, at Infineon in Europe and here in the US certainly all the guys pushing the leading edge of performance in embedded cores as well as in Asia. There is no geographic differentiation.

There is a lot of talk about designs being done in India and China both for domestic consumption and as outsourcing form the US and Europe.
Again I think the industry might be a little bit out over its surfboard with respect to designing. Certainly there is a lot more design work going on in China as opposed to pure manufacturing. Interestingly enough our COO is over there in China this week talking to several companies. There is a trend for more design work to be done in those parts of the world particularly in China and India. We've got one customer who has a very large design facility in India. We expect that to go up certainly in India as well as the rest of Asia.

What about your own development operation? Where is it located?
It's spread around. In this marketplace finding the right people with the right skills at the right time is always a challenge. It's critical for even small companies to make sure that they take the opportunity to find the skills that they need wherever they exist. Today to do geographically dispersed software development is not uncommon. We have people spread all over the place. We are opening a facility in India this quarter. We have people in Europe. So it's spread around.

When we talked about Synchronicity earlier you said that they needed a partner or acquirer with global infrastructure to scale their business. Does this also apply to Zenasis?
I don't think so. The nature of Synchronicity application linking global organizations together implies the need to have support resources, training resources and so forth around the globe. With a technology like Zenasis which is a very focused application on a very specific problem I think the need is somewhat less for having a partner but certainly in order to expand our customer footprint we gain leverage by having the right partners in place - some of the IT providers, the core providers as well as the EDA companies. We will actively seek out partners to grow more rapidly.

Is there any topic we didn't cover that you feel my readers might be interested in?
I'll close by saying that Zenasis is going to be focused on whole product which involves services, documentation and training necessary for the users of our products to deploy it on wide scale basis. We are going to remain focused on helping design teams maximize design performance in less time with lower costs. That's a good place to be because that's a real problem that design teams have today.


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