Celoxica Delivers Support for IEEE SystemC 2.1; Latest Release of Celoxica's Agility Compiler For SystemC Provides SystemC 2.1 Language Support, Comprehensive TLM Synthesis and Ease-Of-Use
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Celoxica Delivers Support for IEEE SystemC 2.1; Latest Release of Celoxica's Agility Compiler For SystemC Provides SystemC 2.1 Language Support, Comprehensive TLM Synthesis and Ease-Of-Use

OXFORDSHIRE, United Kingdom—(BUSINESS WIRE)—Jan. 17, 2006— Celoxica (LSE: CXA) today announced the latest release of its Agility Compiler for SystemC synthesis supporting SystemC prototyping and verification. The new release can generate RTL descriptions from transaction level models (TLM) for popular ASIC/ SoC synthesis flows and gate-level EDIF netlists for programmable logic devices.

SystemC 2.1, now known as IEEE Std.P1666, provides a definitive description and a precise and complete specification of the SystemC language. Implementations can now be confidently developed with reference to the SystemC standard with a common framework for collaboration.

As part of Celoxica's program to improve integration of SystemC simulation and verification with synthesis, designers can now build simulations directly from the Agility Compiler GUI. From the same source code files designers can verify their SystemC designs against the OSCI reference model in a single environment.

"Fundamental to the adoption of SystemC by our customers is standards compliance, ease-of-use and superior QoR targeting custom hardware and high density programmable logic," said Jeff Jussel, vice-president of worldwide marketing for Celoxica. "With the latest release of Agility we have demonstrated our commitment and currency with SystemC and strengthened its capabilities for prototyping, verification and production."

Improved code management and ease-of-use is supported through RAM inferencing and enhanced SystemC datatypes that also allow for better quality of results from less code. Comprehensive feedback is provided to the developer though enhanced design reporting and synthesis analysis. Agility's Control and Dataflow Graph (CDFG) viewer allows the designer to accurately view, analyze and understand high-level designs, linking source code through to synthesis results and interactively browsing a graphical representation of the design.

About Celoxica

A leader in electronic system level design (ESL), Celoxica is enabling the next generation of advanced electronic products by producing tools, boards, IP and services that turn software into silicon. Celoxica technology raises design abstraction to the algorithm level, accelerating productivity and lowering risk and costs by generating semiconductor hardware directly from C-based software descriptions. Adding to a growing installed base, Celoxica provides the world's most widely used C-based behavioral design and synthesis solutions to companies developing semiconductor products in markets such as consumer electronics, defense and aerospace, automotive, industrial and security. Celoxica is a publicly traded company on the Alternative Investment Market of the London Stock Exchange under the symbol CXA. For more information, visit: www.celoxica.com.

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