The new Encounter offerings are tiered into three levels, Encounter L, XL and GXL. The Encounter L product series provides an easy-to-use, integrated, value-priced implementation environment for less complex, flat designs at 150 nanometers and above with gate counts below 5M gates. The Encounter XL product series targets large-scale, high-performance, hierarchical designs over 5M gates at 130, 90 and 65 nanometers, and features MasterPlan automatic macro placement and floorplanning technology. A third series, Encounter GXL, is scheduled for delivery in the fourth quarter of 2005.
The MasterPlan feature within the Encounter XL series reduces the design effort required to design the physical architecture for very complex SoC designs. This includes high-end networking, graphics and processor ICs with hundreds of embedded memories and hard IP blocks which are typically placed manually. Unlike conventional automation approaches that focus strictly on projected wire length, the MasterPlan feature within the Encounter XL series works by optimizing overall chip signal flows. The result is an expert-quality chip plan in a fraction of the time typically taken.
"We have successfully started to use MasterPlan automatic floorplanning in our production designs," said Hisaharu Miwa, Deputy General Manager, Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp. "It allows us to create an automatic floorplan for multi-million gate designs with hundreds or even thousands of hard macros in minutes or hours, as opposed to the days or weeks it formerly took. MasterPlan is key to our goal of reducing overall design cycle time on high-complexity nanometer designs."
"Many complex designs consist of hundreds of hard macros. Automatically creating a floorplan for such designs is a difficult problem," said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 of STARC. "We have been evaluating MasterPlan from the beginning, and we have found that it automatically produces much better initial floorplan results than other existing tools available in the market. Starting with the MasterPlan results, our designers will dramatically shorten turn-around-time to reach the final floorplan. We are looking forward to current and future enhancements of automatic floorplanning features for our production deployment."
"We are excited to bring the latest IC Implementation technology to our customers," said Wei-Jin Dai, corporate vice president, R&D for Cadence. "With MasterPlan automatic floorplanning, the Encounter platform further extends its lead in high-end digital IC design, while the Encounter L series serves the needs of mainstream designers."
The First Encounter(R) L and First Encounter XL silicon virtual prototyping products, and SoC Encounter(TM) L and SoC Encounter XL full implementation products, will be available in September 2005.
About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, First Encounter, Encounter and the Cadence logo are registered trademarks and SoC Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
Contact:
Cadence Design Systems, Inc. Judy Erkanat, 408-894-2302 Email Contact