New Cadence PowerMeter Technology Enables Signoff-Quality Dynamic Power Rail Verification; VoltageStorm Dynamic IR Drop Analysis Enhanced with Sophisticated Power Consumption Analysis Capabilities
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New Cadence PowerMeter Technology Enables Signoff-Quality Dynamic Power Rail Verification; VoltageStorm Dynamic IR Drop Analysis Enhanced with Sophisticated Power Consumption Analysis Capabilities

SAN JOSE, Calif.—(BUSINESS WIRE)—May 25, 2005— Cadence Design Systems, Inc. (NYSE: CDN)(Nasdaq: CDN) today introduced new PowerMeter functionality that extends its dynamic power rail analysis solution with signoff-quality power calculation. Using dynamic power calculation algorithms, PowerMeter enables design teams to accurately calculate and distribute leakage, internal and switching power consumption for every instance of their design.

When used with the Dynamic Gate (DG) option to the market-leading VoltageStorm(R) power analysis solution, PowerMeter calculates the distributed dynamic power used to drive the dynamic rail analysis of a design. This analysis determines the impact of voltage (IR) drop transients on the power and ground rails of a design. Designers can use this information to optimize their power routing widths and the size and location of de-coupling capacitors used to tame IR drop transients, gaining confidence that IR drop will not cause silicon failure.

"We were establishing our 130 nanometer design methodology and wanted to ensure sufficient de-coupling capacitance on our power rails to avoid any significant dynamic IR drop issues," said Noam Benayahu, director of VLSI, Metalink Ltd. "PowerMeter showed us how large transient power consumption spikes, associated with simultaneous switching during our scan testing, resulted in high dynamic IR drop through the power rails. Using VoltageStorm DG, we were able to better optimize both the location and size of our added de-coupling capacitors prior to tapeout."

At and beyond the 130-nanometer process node, static power rail verification methodologies must be complemented with dynamic analysis to consistently achieve working silicon. Designers can control significant IR drop transients on the power rails by adding de-coupling capacitance. However, increased device leakage dictates that added de-coupling capacitors must be carefully optimized to control power consumption.

To help designers address these challenges, VoltageStorm DG uses the new PowerMeter technology to accurately highlight those areas of high simultaneous switching that can cause power rail failure. PowerMeter uses advanced dynamic power analysis algorithms to calculate power waveforms for each of the instances within a cell-based design. Engineers are able to observe large IR drop spikes in both scan and functional modes of operation, and can then adjust their on-chip de-coupling capacitors to address these IR drop transients.

"We wanted to understand the effectiveness of the power rail de-coupling capacitors we added," said Li-Siang Lee, physical design manager at Cortina Design Systems. "VoltageStorm DG's vectorless approach using PowerMeter clearly showed us where power was being consumed, and where we could optimize our capacitance size and locations. We are now confident that IR drop transients will not be a cause of silicon failure for our latest tapeout."

"The new PowerMeter functionality within VoltageStorm DG provides the unmatched accuracy and detail necessary for designers to calculate dynamic power consumption and perform accurate, hierarchical, full-chip power verification," said Dr. Marc Levitt, vice president, Design for Manufacturing at Cadence. "The VoltageStorm family provides a comprehensive power integrity verification solution for all of our customers' design styles, including ASIC, full-custom, analog mixed-signal and system-on-chip (SoC)."

As an integral part of a comprehensive timing analysis flow that is both SI and IR-drop aware, VoltageStorm DG works with Fire & Ice(R) QXC parasitic extraction and CeltIC(R) Nanometer Delay Calculator (NDC) SI-aware delay calculator to enable dynamic timing analysis and noise analysis results that more closely match silicon. VoltageStorm DG creates instance-based operating voltage information read by CeltIC NDC, which then accounts for the reduced operating voltages during both timing and noise analysis.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, CeltIC, Fire & Ice and VoltageStorm are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.



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Cadence Design Systems, Inc.
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