Based on the Cadence(R) Encounter(TM) digital IC platform, this RTL-to-GDSII reference flow will enable higher productivity and improved quality-of-silicon (QoS). The flow will incorporate several innovative Cadence technologies, including Encounter RTL Compiler synthesis, SoC Encounter Global Physical Synthesis (GPS), VoltageStorm(R) Dynamic Gate power rail analysis, and CeltIC(R) Nanometer Delay Calculator (NDC), using the highly accurate effective current source delay model (ECSM) to enable designers to reduce time-to-volume for low-power consumer applications. ARM(R) Artisan(R) Metro(TM) low-power libraries are used for the flow development.
"IBM and Chartered continue to drive a common platform for 90-nanometer designs," said Steve Longoria, vice president, Semiconductor Technology Platform for IBM. "This low-power reference flow is developed in collaboration with Cadence to tackle the complex design challenges of 90 nanometer and below. The combination of the IBM-Chartered 90-nanometer process technologies and Cadence's low-power design methodology will help address the challenges that designers are facing in doing power-efficient IC designs."
"Power management, compressed market windows and the high cost of silicon re-spins are requiring a virtual re-aggregation of the design chain," said Jan Willis, senior vice president, Industry Alliances, at Cadence. "Extending our collaboration with IBM and Chartered in support of their common platform exemplifies how Cadence is working across the design chain to provide solutions to accelerate 90-nanometer design for the mainstream."
"We continue to build on the work we've done with Cadence to develop solutions accelerating our customers' path to silicon while increasing their design productivity," said Kevin Meyer, vice president of worldwide marketing at Chartered. "Cadence is providing advanced low-power technologies for 90-nanometer design that will enable customers to maximize the benefits of technology and choice offered by the common platform."
This reference flow, developed by Cadence Engineering Services, will address critical low-power design concerns, from prototyping through power, timing and area optimization. The Cadence Encounter platform enables timing-aware leakage power and dynamic power optimization, using power techniques such as multi-supply voltages, voltage scaling, clock gating and dual voltage optimization. This optimization helps designers improve timing closure and reduce device area, while lowering power consumption without compromising performance.
"We have been collaborating with Cadence to provide library views based on their ECSM format to more effectively optimize low-power chip designs," said Neal Carney, vice president of Marketing, ARM. "As part of this reference flow, the Artisan low-power platform will incorporate the architectures, circuit designs and low-power features that enable designers to successfully use Cadence's unique chip-level power management techniques to create power-efficient SoCs."
About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, the Cadence logo, CeltIC, Virtuoso and VoltageStorm are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
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