TSMC's 5.0 Reference Flow Implements Apache's RedHawk-SDL for Verification of Dynamic and Static Power Integrity and Global I/O SSO
MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—June 7, 2004— Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) design, today announced that TSMC has adopted RedHawk-SDL as an integral part of its new Reference Flow 5.0, the industry's first reference flow to achieve power closure.Today's industry-leading semiconductor devices contain tens millions of transistors. Hundreds of thousands of these switches may be toggling at any given time, creating highly dynamic power demands that may result in a power integrity issue. RedHawk-SDL provides full-chip dynamic voltage drop analysis and global I/O SSO (Simultaneous-Switching Output) verification, to ensure that all this activity does not compromise the design.
"As process technology moves to 90nm and below, power integrity due to dynamic supply noise has become a key factor in chips meeting frequency, voltage, and yield requirements," said Edward Wan, senior director of design services marketing for TSMC. "By adding Apache's RedHawk-SDL to Reference Flow 5.0, we are able to offer power closure for next-generation SoC designs."
TSMC Reference Flow 5.0 addresses power closure using RedHawk-SDL's full-chip Vectorless Dynamic(TM) power verification suite with cell-based capacity and SPICE-level accuracy. It incorporates the effects of simultaneous switching (core, memory, and I/O), intrinsic and intentional decoupling capacitance, and on-chip and package inductive effects, all of which are neglected by existing static-only analysis solutions. Unlike recently announced pseudo-dynamic approaches that perform sequential static analysis on several sub-windows within a simulation, RedHawk-SDL performs full-chip, true transient, time-point by time-point simulation with built-in SPICE accurate cell characterization of every instance. RedHawk's cell-based static EM/IR-drop capabilities, which provide a static, snap-shot analysis of IR drop, are also supported in Reference Flow 5.0.
As the number of I/O busses and package pins increase, the effects of global I/O SSO is becoming a major source of supply-noise induced chip failure. Apache's global I/O SSO flow is based on RedHawk-SDL's P/G network extraction and NSPICE-PI's large scale mixed-domain SPICE simulation capabilities. TSMC's 5.0 Reference Flow includes Global I/O SSO methodology based on Apache's RedHawk-SDL and NSPICE-PI to address this increasingly important physical power integrity issue, also including package coupling.
"TSMC's advanced process technologies have been driving the most advanced flow requirements and our mutual customers will benefit from the ongoing collaboration to address the critical challenges of power closure," said Andrew Yang, CEO for Apache. "We are finding more and more customers facing chip failures due to dynamic power and global I/O SSO issues. RedHawk-SDL was built to address the power integrity problems associated by dynamic supply noise and we are excited to be part of TSMC's 5.0 Reference Flow and to enable our customers to increase their silicon yield."
Availability
The TSMC 5.0 Reference Flow is available immediately. The TSMC 5.0 Reference Flow provides a complete solution for power closure and includes Apache's RedHawk-SDL and NSPICE-PI for dynamic/static power and global I/O SSO verification.
About RedHawk
Apache's flagship RedHawk fills the critical missing link for physical power flows in 130nm, 90nm, and 65nm system on chip (SoC) designs. RedHawk provides the only full-chip static and Vectorless Dynamic(TM) physical power solution that is capable of addressing dynamic power issues such as simultaneous switching outputs (SSO) for core, memory, clock and I/O, as well as the effects of on-chip inductance, package models, and decoupling capacitance.
RedHawk enables designers to examine the power and timing impact on a chip caused by physical implementation decisions made from the early design stage through final verification. RedHawk delivers full-chip analysis capabilities with transistor-level accuracy, and addresses verification issues associated with low-power techniques such as leakage current, power gating, multiple voltages and multiple thresholds.
About Apache Design Solutions
Apache develops innovative next-generation physical power integrity software that accelerates the design process and guarantees the reliability of massive system-on-chip (SoC) semiconductors operating at gigahertz frequencies. By providing tools for power, timing, and system I/O integrity, Apache enables leading networking, wireless, communication, consumer, and semiconductor companies to develop highly competitive and reliable products. For more information, visit www.apache-da.com.
Apache Design Solutions, RedHawk-SDL, and Vectorless Dynamic are trademarks of Apache Design Solutions Inc. All other trademarks mentioned herein are the property of their respective owners.
Contact:
Apache Design Solutions Inc., Mountain View Yukari Chin, 650-237-5422 Email Contact or Cayenne Communication Michelle Clancy, 252-940-0981 Email Contact