Atrenta's Low Power Product Chosen for Voltage Management; Atrenta's ERC Product Chosen for IC Integration
SAN JOSE, Calif.—(BUSINESS WIRE)—June 7, 2004— Atrenta(R) Inc., the Predictive Analysis Company, announced that Taiwan Semiconductor Manufacturing Company (TSMC), has adopted Atrenta's low power and ERC products as key enabling technologies in the new TSMC Reference Flow 5.0, the industry's first design flow providing power closure and integrated chip-to-package design. Both products are part of the unified Atrenta platform that includes advanced solutions for clock domain analysis, DFT analysis, constraints analysis and automated functional analysis.Atrenta's SpyGlass LP is the industry's first customizable product that helps designers deploy a low power design methodology and techniques at RTL. It provides guidance for reducing power on 90 nanometer designs and below, including low power techniques targeting dynamic power, leakage power, and voltage management challenges.
TSMC has also developed a chip-to-package integration flow that uses SpyGlass ERC, a product that validates a gate-level netlist for a wide range of electrical rules and reports critical electrical design rule violations. The tool enables chip level integration by ensuring that a high quality netlist is taken into the back-end.
"We have been working closely with Atrenta and are impressed with Atrenta's low power and ERC solutions and their rapid response in addressing our issues," said Ed Wan, Director of Design Services Marketing at TSMC. "Incorporating these products into the power closure and the chip integration flows in Reference Flow 5.0 completes these important tasks, enabling designers to achieve faster time to market for their products."
"We are excited to collaborate with TSMC to offer designers key solutions in the area of low power and chip integration to improve design productivity," said John Rizzo, Vice President of Marketing at Atrenta Inc. "Leakage power is a critical concern for designs using advanced process technologies. Atrenta's unique low power solution is the industry's first to address voltage management issues. For chip integration, Atrenta's ERC solution provides a high capacity solution for validating gate-level netlists and making sure that all electrical rule violations are avoided before taking the design into the back-end. Both the low power and ERC solutions are now available within Atrenta's new PeriScope platform."
As we move into the sub-nanometer era, power consumption is turning out to be a major challenge to innovation. Voltage management, enabled by TSMC's advanced Nexsys process technology, offers a key technique to solving power consumption. However, making use of voltage management introduces new challenges to the design process. It is critical that the issues associated with voltage and power domain boundaries are analyzed early in the design. Atrenta's low power product is the industry's leading solution for voltage management issues. It addresses architectural level low power design techniques such as the use of voltage and power domains that have maximum impact on power consumption. SpyGlass LP provides a set of techniques that designers can leverage early in the design cycle to ensure automatic checking and generation of interface logic for designs with multiple voltage and power domains.
As chips grow in size, complexity of integration is a big challenge that needs to be addressed. A clean netlist hand-off into the back-end flow is necessary to avoid costly design iterations. Atrenta's ERC product analyzes Verilog and VHDL gate-level netlists for electrical rule compliance. It reads in Synopsys Liberty Format (.lib) files along with the netlist and traces and reports critical electrical design rule violations such as overloaded drivers, undesired clock interactions, delay-time dependent circuits, and library-specific errors. Since netlist errors may occur at design hand-off, the capability provided by an extensible rule checker such as SpyGlass ERC is essential to lower both the risks and the costs of errors at this important stage of product development.
Unified Environment
When used together, all of Atrenta's advanced solutions for functional verification, constraint analysis, clock domain analysis, DFT analysis and low power optimization can run within a common user interface and unified platform. This, for the first time, enables comprehensive and efficient SoC design and verification at the RT-level. By enabling RTL designers to predict and repair downstream design problems in the front-end design process, Atrenta significantly improves the economics of complex SoC design and prototyping.
About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates one advanced 300mm wafer fab, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at venture fab SSMC and at its wholly-owned subsidiary, WaferTech. TSMC's Nexsys Technology for SoC describes a suite of semiconductor process technologies and foundry services used in advanced technology semiconductor manufacturing. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC see http://www.tsmc.com.
About Atrenta
Atrenta delivers predictive analysis and verification solutions to the world's leading electronics companies, including eight of the top ten semiconductor companies. Its pioneering PeriScope and SpyGlass solutions accelerate the design of SoCs, ASICs, and FPGAs by detecting complex chip design problems that are not easily identified with conventional verification methods. Atrenta's products have been recognized through several distinguished awards, including EDN magazine's Top 100 products and "LSI Design of the Year" award by Japan's Semiconductor Industry News. Most recently, Atrenta's constraints product was named as an EDN Innovation Awards finalist for 2004. Atrenta was also chosen by Venture Reporter as one of the top 100 venture-backed companies, and named by AlwaysOn as one of the Top 100 private companies.
Atrenta, with headquarters in San Jose, California, employs over 150 people worldwide. It has European offices in England and France, a research and development center in India, and sales and support distributors in Europe, India, Israel, Japan, Korea, Singapore, and Taiwan. For further information, visit the Atrenta website at www.atrenta.com, email moreinfo@atrenta.com, or call 408-453-3333.
Atrenta and SpyGlass are registered trademarks and Periscope is a trademark of Atrenta Inc. All other trademarks belong to their respective owners.
Contact:
Atrenta Paula Jones, 650-967-3711 (PR) Email Contact Mona Singh, 408-467-4248 Email Contact