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September 2013
New Meridian and Ascent Product Releases Now Available
Since our May newsletter we have announced new releases of
Meridian CDC,
Ascent Lint and the
Ascent X-Verification System (XV). These releases maintain our best-in-class performance and feature lots of enhancements to accelerate sign-off of your SoCs. More details are below.
Thoughts From Prakash Narain, President and CEO…
There’s a lot of talk these days about RTL sign-off and SoC sign-off. Many people assume these terms are interchangeable. Actually there’s a world of difference between the two. So let’s set the record straight. SoC sign-off – Real Intent’s domain expertise – is the process of ensuring a failure mode will never happen in your design. SoC sign-off must be available at the right time in the flow, and must have the right functionality. You should be able to deploy it at all stages at which you need sign-off. Complete sign-off requires verification at full chip netlists as well as at the register transfer level. A good example of SoC sign-off – the only true sign-off – is our clock domain crossing complete solution, Meridian CDC. In contrast, RTL sign-off is really an enhanced version of linting. Implemented at the RTL, it’s efficient. But that’s not where the problems stop. Today’s increasingly complex designs add a lot more pain to the sign-off process. What used to be 100M-gate designs now are becoming giga-scale in size, with sign-off expected to happen in the same timeframe as before. So it’s not simply about completing a task, but about completing it in the most optimal way. And that’s a value proposition that must be brought into the methodology to keep pace with this added complexity. Minimizing the amount of change per design and increasing dependence on IP integration is vital as new elements are added in. Real Intent understands well that the final burden is on SoC companies for complete sign-off. RTL sign-off simply isn’t enough anymore.
Quick Comment by Michael Martin, Director of Engineering, IDT
“Integrated Design Technology, Inc., the Analog and Digital Company™, develops system-level solutions that optimize its customers' applications. Both Ascent Lint and Meridian CDC from Real Intent are now integral to our production design flow and we have found the products to be very stable, fast and easy to use. In addition, the support from Real Intent across the board has been excellent.”
In June, Real Intent announced the version 5.0 release of its Meridian CDC product for comprehensive clock domain crossing analysis. This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent’s product leadership in the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.
Some of the new features include:
- A new correct-by-configuration design setup to enhance analysis and reporting clarity for clock crossings to ease the sign-off process
- Enriched SDC design constraint support with the addition of clock groups and naming schemes
- “Cleaner and meaner” issue reporting for: bus handling; reset analysis, including glitches in both asynchronous and synchronous domains; and crossings that may be blocked by the design environment
- An enhanced formal analysis engine with greater speed and coverage
Click
here to read further details about the announcement. For additional insights and comments from Sarath Kirihennedige, senior manager of product engineering, please watch a video interview
here.
This month we announced our newly enhanced version of Ascent Lint that delivers enhanced support for SystemVerilog, Verilog and VHDL languages, and improves ease of use in the GUI and low-noise reporting of design issues. A new integrated Emacs-mode feature enables users to view and manage all lint violations at each RTL source location for easier debugging. Users now can edit the source code, manage violations, and rerun Ascent Lint to view updated violations – all from within the Emacs editor.
Further notable enhancements and latest features include:
- 22 new lint rules that ensure design code quality and consistency
- A new CDC Readiness policy that ensures readiness for Clock Domain Crossing analysis
- Extension of regular expression syntax to be Perl-compatible for more flexible processing
Click
here for further announcement details. For additional insights and comments from Shiva Borzin, Technical Marketing Manager, please watch a video interview
here.
New Ascent XV for X-Design and Verification
The new version of Ascent XV delivers significant enhancements for initialization analysis, and the detection and management of unknown logic values (Xs).
SoC sign-off needs sign-off to cover analysis and optimization of design initialization in the presence of Xs. Modern power management schemes affect how designs are initialized and how they transition between different power states. X management and reset analysis are interrelated because many of the Xs in simulation come from uninitialized flip-flops. Ascent XV provides the necessary analysis of initialization sequences to ensure a complete and optimal initialization for various power states in a SoC. It provides the same best-in-class verification performance, as the other Ascent products, for uncovering issues prior to digital simulation and synthesis.
Click
here for further announcement details. For additional insights and comments from Pranav Ashar, Chief Technical Officer, please watch a video interview
here.
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Video Update
SoC Sign-off Needs Analysis and Optimization of Design Initialization in the Presence of Xs
In the News
Real Intent Joins Synopsys in-Sync Program
Upcoming Events
Verify 2013 Seminar, Yokohama, Sept. 27
Formal Methods in CAD, Portland, OR, Oct. 23
ARM TechCon,
Santa Clara, Oct. 30-31
SemIsrael Expo, Nov. 18
Verification Futures, Munich, Nov. 18,
Reading, UK, Nov. 19
EDSFair, Yokohama,
Nov. 20-22
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