Memoir Systems’ Renaissance™ 2x and Renaissance 4x memory IP now available for TSMC’s Physical Memory Libraries

SAN JOSE, Calif. — (BUSINESS WIRE) — April 2, 2013 — Memoir Systems:

Type:		Industry Conference
Date:		9 April, 2013
Location:		San Jose, CA

The TSMC 2013 North American Technology Symposium delivers updates on TSMC’s advanced technologies, advanced back-end capabilities and future plans.

Memoir Systems is participating in the TSMC Symposium for the first time this year. The company will demonstrate how its Renaissance memory IP products can be used in combination with TSMC’s physical memory libraries to create higher performance memories. This demonstration will also highlight the area and power savings that can be achieved for practically any SoC implementation with Memoir’s product solutions.

Based upon the company’s award-winning patented Algorithmic Memory® technology, Renaissance memory IP increases the memory performance of existing embedded memory macros by delivering up to a 4x increase in memory operations per second (MOPS). In addition, it eliminates the need to build custom multiport memories and can reduce area and power requirements by up to 60% compared to conventional physical multiport implementations.

Who should attend?

System architects, engineers, engineering managers and executives who seek more information about the integration of Memoir’s Renaissance memory IP with TSMC libraries are invited to visit Memoir Systems at booth 201.

Questions about this event?

Send email to Kella Knack ( Email Contact)

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Contact:

KJ Communications
Kella Knack, 707-568-3502
Email Contact